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r01ds0018ej0110 rev.1.10 page 1 of 59 nov 02, 2010 r8c/36c group renesas mcu datasheet 1. overview 1.1 features the r8c/36c group of single-chip mcus incorporates the r8c cpu core, employing sophisticated instructions for a high level of efficiency. with 1 mbyte of address space, and it is capable of executing instructions at high speed. in addition, the cpu core boasts a multiplier for high-speed operation processing. power consumption is low, and the supported operating modes allow additional power control. these mcus are designed to maximize emi/ems performance. integration of many peripheral functions, including multifun ction timer and serial inte rface, reduces the number of system components. the r8c/36c group has data flash (1 kb 4 blocks) with the background operation (bgo) function. 1.1.1 applications electronic household appliances, office equipment, audio equipment, cons umer equipment, etc. r01ds0018ej0110 rev.1.10 nov 02, 2010
r8c/36c group 1. overview r01ds0018ej0110 rev.1.10 page 2 of 59 nov 02, 2010 1.1.2 specifications tables 1.1 and 1.2 outline the specifications for r8c/36c group. table 1.1 specifications for r8c/36c group (1) item function specification cpu central processing unit r8c cpu core ? number of fundamental instructions: 89 ? minimum instruction execution time: 50 ns (f(xin) = 20 mhz, vcc = 2.7 to 5.5 v) 200 ns (f(xin) = 5 mhz, vcc = 1.8 to 5.5 v) ? multiplier: 16 bits 16 bits 32 bits ? multiply-accumulate instruction: 16 bits 16 bits + 32 bits 32 bits ? operation mode: single-chip mode (address space: 1 mbyte) memory rom, ram, data flash refer to table 1.3 product list for r8c/36c group power supply voltage detection voltage detection circuit ? power-on reset ? voltage detection 3 (detection level of voltage detection 0 and voltage detection 1 selectable) i/o ports programmable i/o ports ? input-only: 1 pin ? cmos i/o ports: 59, se lectable pull-up resistor ? high current drive ports: 59 clock clock generation circuits ? 4 circuits: xin clock oscillation circuit, xcin clock oscillation circuit (32 khz), high-speed on-chip oscillator (with frequency adjustment function), low-speed on-chip oscillator ? oscillation stop detection: xin cl ock oscillation stop detection function ? frequency divider circuit: dividing selectable 1, 2, 4, 8, and 16 ? low power consumption modes: standard operating mode (high-speed clock, low-speed clock, high-speed on- chip oscillator, low-speed on-chip oscillator), wait mode, stop mode real-time clock (timer re) interrupts ? interr upt vectors: 69 ? external: 9 sources (int 5, key input 4) ? priority levels: 7 levels watchdog timer ? 14 bits 1 (with prescaler) ? reset start selectable ? low-speed on-chip oscillator for watchdog timer selectable dtc (data transfer controller) ? 1 channel ? activation sources: 39 ? transfer modes: 2 (normal mode, repeat mode) timer timer ra 8 bits 1 (with 8-bit prescaler) timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse wi dth measurement mode, pulse period measurement mode timer rb 8 bits 1 (with 8-bit prescaler) timer mode (period timer), programmable waveform generation mode (pwm output), programmable one-shot gene ration mode, programmable wait one- shot generation mode timer rc 16 bits 1 (with 4 capture/compare registers) timer mode (input capture function, output compare function), pwm mode (output 3 pins), pwm2 mode (pwm output pin) timer rd 16 bits 2 (with 4 capture/compare registers) timer mode (input capture function, output compare function), pwm mode (output 6 pins), reset synchronous pwm mode (output three-phase waveforms (6 pins), sawtooth wave modulation), complementary pwm mode (output three-phase waveforms (6 pins), triangular wave modulation), pwm3 mode (pwm output 2 pins with fixed period)
r8c/36c group 1. overview r01ds0018ej0110 rev.1.10 page 3 of 59 nov 02, 2010 note: 1. specify the d version if d version functions are to be used. table 1.2 specifications for r8c/36c group (2) item function specification timer timer re 8 bits 1 real-time clock mode (count seconds, minu tes, hours, days of week), output compare mode timer rf 16 bits 1 input capture mode (input capture ci rcuit), output compare mode (output compare circuit) timer rg 16 bits 1 (with 2 capture/compare registers) timer mode (input capture function, output compare function), pwm mode (output 1 pin), phase counting mode (available automatic measurement for the counts of 2-phase encoder) serial interface uart0, uart1 clock synchronous serial i/o/uart 2 channel uart2 clock synchronous serial i/o, uart, i 2 c mode (i 2 c bus), multiprocessor communication function synchronous serial communication unit (ssu) 1 (shared with i 2 c bus) i 2 c bus 1 (shared with ssu) lin module hardware lin: 1 (timer ra, uart0) a/d converter 10-bit resolution 12 channels, includes sample and hold function, with sweep mode d/a converter 8-bit resolution 2 circuits comparator b 2 circuits flash memory ? programming and erasur e voltage: vcc = 2.7 to 5.5 v ? programming and erasure endur ance:10,000 times (data flash) 1,000 times (program rom) ? program security: rom code protect, id code check ? debug functions: on-chip debug, on -board flash rewrite function ? background operation (bgo) function (data flash) operating frequency/supply voltage f(xin) = 20 mhz (vcc = 2.7 to 5.5 v) f(xin) = 5 mhz (vcc = 1.8 to 5.5 v) current consumption typ. 7.0 ma (v cc = 5.0 v, f(xin) = 20 mhz) typ. 3.5 ma (vcc = 3.0 v, f(xin) = 10 mhz) typ. 4.0 a (vcc = 3.0 v, wait mode (f(xcin) = 32 khz)) typ. 2.0 a (vcc = 3.0 v, stop mode) operating ambient temperature ? 20 to 85 c (n version) ? 40 to 85 c (d version) (1) package 64-pin lqfp ? package code: plqp0064kb- a (previous code: 64p6q-a) ? package code: plqp0064ga-a (previous code: 64p6u-a) 64-pin tqfp ? package code: ptqp0064lb-a
r8c/36c group 1. overview r01ds0018ej0110 rev.1.10 page 4 of 59 nov 02, 2010 1.2 product list tables 1.3 and 1.4 list product list for r8c/36c group. figure 1.1 shows a part number, memory size, and package of r8c/36c group. (d): under development note: 1. the user rom is programmed before shipment. table 1.3 product list for r8c/36c group (1) current of nov 2010 part no. rom capacity ram capacity package type remarks program rom data flash r5f21364cnfp 16 kbytes 1 kbyte 4 1 .5 kbytes plqp0064kb-a n version r5f21365cnfp 24 kbytes 1 kbyt e 4 2 kbytes plqp0064kb-a r5f21366cnfp 32 kbytes 1 kbyte 4 2.5 kbytes plqp0064kb-a r5f21367cnfp 48 kbytes 1 kbyt e 4 4 kbytes plqp0064kb-a r5f21368cnfp 64 kbytes 1 kbyt e 4 6 kbytes plqp0064kb-a r5f2136acnfp 96 kbytes 1 kbyt e 4 8 kbytes plqp0064kb-a R5F2136CCNFP 128 kbytes 1 kbyte 4 10 kbytes plqp0064kb-a r5f21364cnfa 16 kbytes 1 kbyte 4 1.5 kbytes plqp0064ga-a r5f21365cnfa 24 kbytes 1 kbyte 4 2 kbytes plqp0064ga-a r5f21366cnfa 32 kbytes 1 kbyte 4 2.5 kbytes plqp0064ga-a r5f21367cnfa 48 kbytes 1 kbyte 4 4 kbytes plqp0064ga-a r5f21368cnfa 64 kbytes 1 kbyte 4 6 kbytes plqp0064ga-a r5f2136acnfa 96 kbytes 1 kbyt e 4 8 kbytes plqp0064ga-a r5f2136ccnfa 128 kbytes 1 kbyte 4 10 kbytes plqp0064ga-a r5f21364cnfb (d) 16 kbytes 1 kbyte 4 1.5 kbytes ptqp0064lb-a r5f21365cnfb (d) 24 kbytes 1 kbyte 4 2 kbytes ptqp0064lb-a r5f21366cnfb (d) 32 kbytes 1 kbyte 4 2.5 kbytes ptqp0064lb-a r5f21367cnfb (d) 48 kbytes 1 kbyte 4 4 kbytes ptqp0064lb-a r5f21368cnfb (d) 64 kbytes 1 kbyte 4 6 kbytes ptqp0064lb-a r5f2136acnfb (d) 96 kbytes 1 kbyte 4 8 kbytes ptqp0064lb-a r5f2136ccnfb (d) 128 kbytes 1 kbyte 4 10 kbytes ptqp0064lb-a r5f21364cnxxxfp 16 kbytes 1 kbyte 4 1.5 kbytes plqp0064kb-a n version factory programming product (1) r5f21365cnxxxfp 24 kbytes 1 kbyte 4 2 kbytes plqp0064kb-a r5f21366cnxxxfp 32 kbytes 1 kbyt e 4 2.5 kbytes plqp0064kb-a r5f21367cnxxxfp 48 kbytes 1 kbyte 4 4 kbytes plqp0064kb-a r5f21368cnxxxfp 64 kbytes 1 kbyte 4 6 kbytes plqp0064kb-a r5f2136acnxxxfp 96 kbytes 1 kbyt e 4 8 kbytes plqp0064kb-a r5f2136ccnxxxfp 128 kbytes 1 kb yte 4 10 kbyt es plqp0064kb-a r5f21364cnxxxfa 16 kbytes 1 kbyte 4 1.5 kbytes plqp0064ga-a r5f21365cnxxxfa 24 kbytes 1 kbyte 4 2 kbytes plqp0064ga-a r5f21366cnxxxfa 32 kbytes 1 kbyte 4 2.5 kbytes plqp0064ga-a r5f21367cnxxxfa 48 kbytes 1 kbyte 4 4 kbytes plqp0064ga-a r5f21368cnxxxfa 64 kbytes 1 kbyte 4 6 kbytes plqp0064ga-a r5f2136acnxxxfa 96 kbytes 1 kbyt e 4 8 kbytes plqp0064ga-a r5f2136ccnxxxfa 128 kbytes 1 kb yte 4 10 kbyt es plqp0064ga-a r5f21364cnxxxfb (d) 16 kbytes 1 kbyte 4 1.5 kbytes ptqp0064lb-a r5f21365cnxxxfb (d) 24 kbytes 1 kbyte 4 2 kbytes ptqp0064lb-a r5f21366cnxxxfb (d) 32 kbytes 1 kbyte 4 2.5 kbytes ptqp0064lb-a r5f21367cnxxxfb (d) 48 kbytes 1 kbyte 4 4 kbytes ptqp0064lb-a r5f21368cnxxxfb (d) 64 kbytes 1 kbyte 4 6 kbytes ptqp0064lb-a r5f2136acnxxxfb (d) 96 kbytes 1 kb yte 4 8 kbytes ptqp0064lb-a r5f2136ccnxxxfb (d) 128 kbytes 1 kbyte 4 10 kbytes ptqp0064lb-a
r8c/36c group 1. overview r01ds0018ej0110 rev.1.10 page 5 of 59 nov 02, 2010 (d): under development note: 1. the user rom is programmed before shipment. table 1.4 product list for r8c/36c group (2) current of nov 2010 part no. rom capacity ram capacity package type remarks program rom data flash r5f21364cdfp 16 kbytes 1 kbyte 4 1 .5 kbytes plqp0064kb-a d version r5f21365cdfp 24 kbytes 1 kbyt e 4 2 kbytes plqp0064kb-a r5f21366cdfp 32 kbytes 1 kbyte 4 2.5 kbytes plqp0064kb-a r5f21367cdfp 48 kbytes 1 kbyt e 4 4 kbytes plqp0064kb-a r5f21368cdfp 64 kbytes 1 kbyt e 4 6 kbytes plqp0064kb-a r5f2136acdfp 96 kbytes 1 kbyt e 4 8 kbytes plqp0064kb-a r5f2136ccdfp 128 kbytes 1 kbyte 4 10 kbytes plqp0064kb-a r5f21364cdfa 16 kbytes 1 kbyte 4 1.5 kbytes plqp0064ga-a r5f21365cdfa 24 kbytes 1 kbyte 4 2 kbytes plqp0064ga-a r5f21366cdfa 32 kbytes 1 kbyte 4 2.5 kbytes plqp0064ga-a r5f21367cdfa 48 kbytes 1 kbyte 4 4 kbytes plqp0064ga-a r5f21368cdfa 64 kbytes 1 kbyte 4 6 kbytes plqp0064ga-a r5f2136acdfa 96 kbytes 1 kbyt e 4 8 kbytes plqp0064ga-a r5f2136ccdfa 128 kbytes 1 kbyte 4 10 kbytes plqp0064ga-a r5f21364cdfb (d) 16 kbytes 1 kbyte 4 1.5 kbytes ptqp0064lb-a r5f21365cdfb (d) 24 kbytes 1 kbyte 4 2 kbytes ptqp0064lb-a r5f21366cdfb (d) 32 kbytes 1 kbyte 4 2.5 kbytes ptqp0064lb-a r5f21367cdfb (d) 48 kbytes 1 kbyte 4 4 kbytes ptqp0064lb-a r5f21368cdfb (d) 64 kbytes 1 kbyte 4 6 kbytes ptqp0064lb-a r5f2136acdfb (d) 96 kbytes 1 kbyte 4 8 kbytes ptqp0064lb-a r5f2136ccdfb (d) 128 kbytes 1 kbyte 4 10 kbytes ptqp0064lb-a r5f21364cdxxxfp 16 kbytes 1 kbyte 4 1.5 kbytes plqp0064kb-a n version factory programming product r5f21365cdxxxfp 24 kbytes 1 kbyte 4 2 kbytes plqp0064kb-a r5f21366cdxxxfp 32 kbytes 1 kbyt e 4 2.5 kbytes plqp0064kb-a r5f21367cdxxxfp 48 kbytes 1 kbyte 4 4 kbytes plqp0064kb-a r5f21368cdxxxfp 64 kbytes 1 kbyte 4 6 kbytes plqp0064kb-a r5f2136acdxxxfp 96 kbytes 1 kbyt e 4 8 kbytes plqp0064kb-a r5f2136ccdxxxfp 128 kbytes 1 kb yte 4 10 kbyt es plqp0064kb-a r5f21364cdxxxfa 16 kbytes 1 kbyte 4 1.5 kbytes plqp0064ga-a r5f21365cdxxxfa 24 kbytes 1 kbyte 4 2 kbytes plqp0064ga-a r5f21366cdxxxfa 32 kbytes 1 kbyte 4 2.5 kbytes plqp0064ga-a r5f21367cdxxxfa 48 kbytes 1 kbyte 4 4 kbytes plqp0064ga-a r5f21368cdxxxfa 64 kbytes 1 kbyte 4 6 kbytes plqp0064ga-a r5f2136acdxxxfa 96 kbytes 1 kbyt e 4 8 kbytes plqp0064ga-a r5f2136ccdxxxfa 128 kbytes 1 kb yte 4 10 kbyt es plqp0064ga-a r5f21364cdxxxfb (d) 16 kbytes 1 kbyte 4 1.5 kbytes ptqp0064lb-a r5f21365cdxxxfb (d) 24 kbytes 1 kbyte 4 2 kbytes ptqp0064lb-a r5f21366cdxxxfb (d) 32 kbytes 1 kbyte 4 2.5 kbytes ptqp0064lb-a r5f21367cdxxxfb (d) 48 kbytes 1 kbyte 4 4 kbytes ptqp0064lb-a r5f21368cdxxxfb (d) 64 kbytes 1 kbyte 4 6 kbytes ptqp0064lb-a r5f2136acdxxxfb (d) 96 kbytes 1 kb yte 4 8 kbytes ptqp0064lb-a r5f2136ccdxxxfb (d) 128 kbytes 1 kbyte 4 10 kbytes ptqp0064lb-a
r8c/36c group 1. overview r01ds0018ej0110 rev.1.10 page 6 of 59 nov 02, 2010 figure 1.1 part number, memory size, and package of r8c/36c group part no. r 5 f 21 36 6 c n xxx fp package type: fp: plqp0064kb-a fa: plqp0064ga-a fb: ptqp0064lb-a rom number classification n: operating ambient temperature ? 20c to 85c d: operating ambient temperature ? 40c to 85c rom capacity 4: 16 kb 5: 24 kb 6: 32 kb 7: 48 kb 8: 64 kb a: 96 kb c: 128 kb r8c/36c group r8c/3x series memory type f: flash memory renesas mcu renesas semiconductor
r8c/36c group 1. overview r01ds0018ej0110 rev.1.10 page 7 of 59 nov 02, 2010 1.3 block diagram figure 1.2 shows a block diagram. figure 1.2 block diagram d/a converter (8 bits 2) r8c cpu core system clock generation circuit xin-xout high-speed on-chip oscillator low-speed on-chip oscillator xcin-xcout memory rom (1) ram (2) multiplier r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o ports notes: 1. rom size varies with mcu type. 2. ram size varies with mcu type. timers timer ra (8 bits 1) timer rb (8 bits 1) timer rc (16 bits 1) timer rd (16 bits 2) timer re (8 bits 1) timer rf (16 bits 1) timer rg (16 bits 1) uart or clock synchronous serial i/o (8 bits 3) i 2 c bus or ssu (8 bits 1) peripheral functions watchdog timer (14 bits) a/d converter (10 bits 12 channels) lin module comparator b voltage detection circuit dtc low-speed on-chip oscillator for watchdog timer 7 port p5 5 1 port p4 8 port p3 8 port p0 8 port p1 8 port p2 8 port p6 7 port p8
r8c/36c group 1. overview r01ds0018ej0110 rev.1.10 page 8 of 59 nov 02, 2010 1.4 pin assignment figure 1.3 shows pin assignment (top view). tables 1.5 and 1.6 outline the pin name information by pin number. figure 1.3 pin assignment (top view) 43 42 41 40 39 38 37 36 24 17 18 19 20 21 22 23 1 3456789101112 2 35 34 33 13 14 15 16 25 26 27 28 29 30 31 32 44 45 46 47 48 r8c/36c group plqp0064kb-a (64p6q-a) plqp0064ga-a (64p6u-a) ptqp0064lb-a (top view) p0_7/an0/da1(/trcioc) p0_6/an1/da0(/trciod) p0_5/an2(/trciob) p0_4/an3/treo(/trciob) p0_3/an4(/clk1/trciob) p0_2/an5(/rxd1/trcioa/trctrg) p0_1/an6(/txd1/trcioa/trctrg) p0_0/an7(/trcioa/trctrg) p6_4(/rxd1) p6_3(/txd1) p6_2(/clk1) p6_1 p6_0(/treo) p5_7(/trgiob) p5_6(/trao/trgioa) p3_2(/int1/int2/traio/trgclkb) p8_4(/trfo11) p8_5(/trfo12) p8_6 p3_1(/trbo) p3_6(/int1) p2_0(/int1/trciob/trdioa0/trdclk) p2_1(/trcioc/trdioc0) p2_2(/trciod/trdiob0) p2_3(/trdiod0) p2_4(/trdioa1) p2_5(/trdiob1) p2_6(/trdioc1) p2_7(/trdiod1) p3_3/ivcmp3/int3/scs(/cts2/rts2/trcclk) p3_4/ivref3/ssi(/rxd2/scl2/txd2/sda2/trcioc) p3_5/scl/ssck(/clk2/trciod) p3_0(/trao/trgclka) p4_2/vref mode p4_3(/xcin) p4_4(/xcout) reset p4_7/xout vss/avss p4_6/xin vcc/avcc p5_4(/trciod) p5_3(/trcioc) p5_2(/trciob) p5_1(/trcioa/trctrg) p5_0(/trcclk) p3_7/sda/sso/trao(/rxd2/scl2/txd2/sda2) p1_0/an8/ki0(/trciod) p1_1/an9/ki1(/trcioa/trctrg) p1_2/an10/ki2(/trciob) p1_3/an11/ki3/trbo(/trcioc) p1_4(/txd0/trcclk) p1_5(/int1/rxd0/traio) p1_6/ivref1(/clk0) p1_7/ivcmp1/int1(/traio) p4_5/adtrg/int0(/rxd2/scl2) p6_5/int4(/clk1/clk2/trciob) p6_6/int2(/txd2/sda2/trcioc) p6_7(/int3/trciod) p8_0(/trfo00) p8_1(/trfo01) p8_2(/trfo02) p8_3(/trfi/trfo10) notes: 1. can be assigned to the pin in parentheses by a program. 2. p4_2 is an input-only pin. 3. confirm the pin 1 position on the package by referring to the package dimensions. 60 59 58 57 56 55 54 53 52 51 50 49 61 62 63 64
r8c/36c group 1. overview r01ds0018ej0110 rev.1.10 page 9 of 59 nov 02, 2010 note: 1. can be assigned to the pin in parentheses by a program. table 1.5 pin name information by pin number (1) pin number control pin port i/o pin functions for peripheral modules interrupt timer serial interface ssu i 2 c bus a/d converter, d/a converter, comparator b 1 p3_0 (trao/trgclka) 2p4_2 vref 3mode 4(xcin)p4_3 5(xcout)p4_4 6 reset 7xout p4_7 8 vss/avss 9xinp4_6 10 vcc/avcc 11 p5_4 (trciod) 12 p5_3 (trcioc) 13 p5_2 (trciob) 14 p5_1 (trcioa/trctrg) 15 p5_0 (trcclk) 16 p3_7 trao (txd2/sda2/ rxd2/scl2) sso sda 17 p3_5 (trciod) (clk2) ssck scl 18 p3_4 (trcioc) (txd2/sda2/ rxd2/scl2) ssi ivref3 19 p3_3 int3 (trcclk) (cts2 /rts2 )scs ivcmp3 20 p2_7 (trdiod1) 21 p2_6 (trdioc1) 22 p2_5 (trdiob1) 23 p2_4 (trdioa1) 24 p2_3 (trdiod0) 25 p2_2 (trciod/trdiob0) 26 p2_1 (trcioc/trdioc0) 27 p2_0 (int1 ) (trciob/trdioa0/ trdclk) 28 p3_6 (int1 ) 29 p3_1 (trbo) 30 p8_6 31 p8_5 (trfo12) 32 p8_4 (trfo11) 33 p8_3 (trfi/trfo10) 34 p8_2 (trfo02) 35 p8_1 (trfo01) 36 p8_0 (trfo00) 37 p6_7 (int3 ) (trciod) 38 p6_6 int2 (trcioc) (txd2/sda2) 39 p6_5 int4 (trciob) (clk2/clk1)
r8c/36c group 1. overview r01ds0018ej0110 rev.1.10 page 10 of 59 nov 02, 2010 note: 1. can be assigned to the pin in parentheses by a program. table 1.6 pin name information by pin number (2) pin number control pin port i/o pin functions for peripheral modules interrupt timer serial interface ssu i 2 c bus a/d converter, d/a converter, comparator b 40 p4_5 int0 (rxd2/scl2) adtrg 41 p1_7 int1 (traio) ivcmp1 42 p1_6 (clk0) ivref1 43 p1_5 (int1 ) (traio) (rxd0) 44 p1_4 (trcclk) (txd0) 45 p1_3 ki3 trbo (/trcioc) an11 46 p1_2 ki2 (trciob) an10 47 p1_1 ki1 (trcioa/trctrg) an9 48 p1_0 ki0 (trciod) an8 49 p0_7 (trcioc) an0/da1 50 p0_6 (trciod) an1/da0 51 p0_5 (trciob) an2 52 p0_4 treo(/trciob) an3 53 p0_3 (trciob) (clk1) an4 54 p0_2 (trcioa/trctrg) (rxd1) an5 55 p0_1 (trcioa/trctrg) (txd1) an6 56 p0_0 (trcioa/trctrg) an7 57 p6_4 (rxd1) 58 p6_3 (txd1) 59 p6_2 (clk1) 60 p6_1 61 p6_0 (treo) 62 p5_7 (trgiob) 63 p5_6 (trao/trgioa) 64 p3_2 (int1 / int2 ) (traio/trgclkb)
r8c/36c group 1. overview r01ds0018ej0110 rev.1.10 page 11 of 59 nov 02, 2010 1.5 pin functions tables 1.7 and 1.8 list pin functions. i: input o: output i/o: input and output note: 1. refer to the oscillator manufactur er for oscillation characteristics. table 1.7 pin functions (1) item pin name i/o type description power supply input vcc, vss ? apply 1.8 to 5.5 v to the vcc pin. apply 0 v to the vss pin. analog power supply input avcc, avss ? power supply for the a/d converter. connect a capacitor between avcc and avss. reset input reset i input ?l? on this pin resets the mcu. mode mode i connect this pin to vcc via a resistor. xin clock input xin i these pins are provid ed for xin clock generation circuit i/o. connect a ceramic resonator or a crystal oscillator between the xin and xout pins. (1) to use an external clock, input it to the xout pin and leave the xin pin open. xin clock output xout i/o xcin clock input xcin i these pins are provided for xcin clock generation circuit i/o. connect a crystal oscillator between the xcin and xcout pins. (1) to use an external clock, input it to the xcin pin and leave the xcout pin open. xcin clock output xcout o int interrupt input int0 to int4 i int interrupt input pins. key input interrupt ki0 to ki3 i key input interrupt input pins. timer ra traio i/o timer ra i/o pin. trao o timer ra output pin. timer rb trbo o timer rb output pin. timer rc trcclk i external clock input pin. trctrg i external trigger input pin. trcioa, trciob, trcioc, trciod i/o timer rc i/o pins. timer rd trdioa0, trdioa1, trdiob0, trdiob1, trdioc0, trdioc1, trdiod0, trdiod1 i/o timer rd i/o pins. trdclk i external clock input pin. timer re treo o divided clock output pin. timer rf trfo00, trfo10, trfo01,trfo11, trfo02,trfo12 o timer rf output pins. trfi i timer rf input pin. timer rg trgioa, trgiob i/o timer rg i/o ports. trgclka, trgclkb i external clock input pins. serial interface clk0, clk1, clk2 i/o transfer clock i/o pins. rxd0, rxd1, rxd2 i serial data input pins. txd0, txd1, txd2 o serial data output pins. cts2 i transmission control input pin. rts2 o reception control output pin. scl2 i/o i 2 c mode clock i/o pin. sda2 i/o i 2 c mode data i/o pin.
r8c/36c group 1. overview r01ds0018ej0110 rev.1.10 page 12 of 59 nov 02, 2010 i: input o: output i/o: input and output table 1.8 pin functions (2) item pin name i/o type description ssu ssi i/o data i/o pin. scs i/o chip-select signal i/o pin. ssck i/o clock i/o pin. sso i/o data i/o pin. i 2 c bus scl i/o clock i/o pin sda i/o data i/o pin reference voltage input vref i reference voltage input pin to a/d converter. a/d converter an0 to an11 i analog input pins to a/d converter. adtrg i ad external trigger input pin. d/a converter da0, da1 o d/a converter output pins. comparator b ivcmp1, ivcmp3 i comparator b analog voltage input pins. ivref1, ivref3 i comparator b reference voltage input pins. i/o port p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_3 to p4_7, p5_0 to p5_4, p5_6, p5_7, p6_0 to p6_7, p8_0 to p8_6 i/o cmos i/o ports. each port has an i/o select direction register, allowing each pin in the port to be directed for input or output individually. any port set to input can be set to use a pull-up resistor or not by a program. input port p4_2 i input-only port.
r8c/36c group 2. central processing unit (cpu) r01ds0018ej0110 rev.1.10 page 13 of 59 nov 02, 2010 2. central processing unit (cpu) figure 2.1 shows the cpu registers. th e cpu contains 13 registers. r0, r1 , r2, r3, a0, a1, and fb configure a register bank. there are two sets of register bank. figure 2.1 cpu registers r2 b31 b15 b8b7 b0 data registers (1) address registers (1) r3 r0h (high-order of r0) r2 r3 a0 a1 intbh b15 b19 b0 intbl fb frame base register (1) the 4 high order bits of intb are intbh and the 16 low order bits of intb are intbl. interrupt table register b19 b0 usp program counter isp sb user stack pointer interrupt stack pointer static base register pc flg flag register carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved bit processor interrupt priority level reserved bit c ipl d z s b o i u b15 b0 b15 b0 b15 b0 b8 b7 note: 1. these registers comprise a register bank. there are two register banks. r1h (high-order of r1) r0l (low-order of r0) r1l (low-order of r1)
r8c/36c group 2. central processing unit (cpu) r01ds0018ej0110 rev.1.10 page 14 of 59 nov 02, 2010 2.1 data registers (r 0, r1, r2, and r3) r0 is a 16-bit register for transfer, ar ithmetic, and logic operations. the same applies to r1 to r3. r0 can be split into high-order bits (r0h) and low-order bits (r0l) to be used separately as 8-bit data registers. r1h and r1l are analogous to r0h and r0l. r2 can be combined with r0 and used as a 32-bit data register (r2r0). r3r1 is analogous to r2r0. 2.2 address regist ers (a0 and a1) a0 is a 16-bit register for address register indirect addr essing and address register relative addressing. it is also used for transfer, arithmetic, and logic operations. a1 is an alogous to a0. a1 can be comb ined with a0 and as a 32- bit address register (a1a0). 2.3 frame base register (fb) fb is a 16-bit register for fb relative addressing. 2.4 interrupt table register (intb) intb is a 20-bit register that indicates the starting address of an interrupt vector table. 2.5 program counter (pc) pc is 20 bits wide and indicates the address of the next instruction to be executed. 2.6 user stack pointer (usp) and interrupt stack pointer (isp) the stack pointers (sp), usp and isp, are each 16 bits wide. the u flag of flg is used to switch between usp and isp. 2.7 static base register (sb) sb is a 16-bit register for sb relative addressing. 2.8 flag register (flg) flg is an 11-bit register indicating the cpu state. 2.8.1 carry flag (c) the c flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit. 2.8.2 debug flag (d) the d flag is for debugging only. set it to 0. 2.8.3 zero flag (z) the z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 sign flag (s) the s flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0. 2.8.5 register bank select flag (b) register bank 0 is selected when the b flag is 0. regi ster bank 1 is selected when this flag is set to 1. 2.8.6 overflow flag (o) the o flag is set to 1 when an operati on results in an overflow; otherwise to 0.
r8c/36c group 2. central processing unit (cpu) r01ds0018ej0110 rev.1.10 page 15 of 59 nov 02, 2010 2.8.7 interrupt enable flag (i) the i flag enables maskable interrupts. interrupts are disabled when the i flag is set to 0, and are enabled when th e i flag is set to 1. the i flag is set to 0 when an interrupt request is acknowledged. 2.8.8 stack pointer select flag (u) isp is selected when the u flag is set to 0; usp is selected when the u flag is set to 1. the u flag is set to 0 when a hardware interrupt reque st is acknowledged or the int instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is 3 bits wide and assigns processor interr upt priority levels from level 0 to level 7. if a requested interrupt has higher priori ty than ipl, the interrupt is enabled. 2.8.10 reserved bit if necessary, set to 0. when read, the conten t is undefined.
r8c/36c group 3. memory r01ds0018ej0110 rev.1.10 page 16 of 59 nov 02, 2010 3. memory 3.1 r8c/36c group figure 3.1 is a memory map of r8c/36c group. the r8 c/36c group has a 1-mbyte a ddress space from addresses 00000h to fffffh. the internal rom (program rom) is allocated lower addresses, beginning with address 0ffffh. for example, a 64-kbyte internal rom area is allocated addresses 04000h to 13fffh. the fixed interrupt vector table is allocated addresses 0ffdch to 0ffffh. the starting address of each interrupt routine is stored here. the internal rom (data flash) is al located addresses 03000h to 03fffh. the internal ram is allocated higher addresses, beginni ng with address 00400h. for example, a 6-kbyte internal ram area is allocated addresse s 00400h to 01bffh. the internal ram is used not only for data storage but also as a stack area when a subroutine is called or when an interrupt request is acknowledged. special function registers (sfr s) are allocated addresses 00000h to 002ffh and 02c00h to 02fffh (the sfr areas for the dtc and other modules). peripheral function contro l registers are allocated here. all unallocated spaces within the sfrs are reserved and cannot be accessed by users.
r8c/36c group 3. memory r01ds0018ej0110 rev.1.10 page 17 of 59 nov 02, 2010 figure 3.1 memory map of r8c/36c group 0ffffh 0ffdch notes: 1. the data flash indicates block a (1 kbyte), block b (1 kbyte), block c (1 kbyte), and block d (1 kbyte). 2. the sfr areas for the dtc and other modules are allocated to addresses 02c00h to 02fffh. 3. the blank areas are reserved and cannot be accessed by users. internal ram size address 0xxxxh 1.5 kbytes 2 kbytes 2.5 kbytes 4 kbytes 6 kbytes 8 kbytes 10 kbytes 009ffh 00bffh 00dffh 013ffh 01bffh 023ffh 02bffh part number internal rom size address 0yyyyh r5f21364cnfp, r5f21364cdfp, r5f21364cnfa, r5f21364cdfa, r5f21364cnfb, r5f21364cdfb, r5f21364cnxxxfp, r5f21364cdxxxfp, r5f21364cnxxxfa, r5f21364cdxxxfa, r5f21364cnxxxfb, r5f21364cdxxxfb r5f21365cnfp, r5f21365cdfp, r5f21365cnfa, r5f21365cdfa, r5f21365cnfb, r5f21365cdfb, r5f21365cnxxxfp, r5f21365cdxxxfp, r5f21365cnxxxfa, r5f21365cdxxxfa, r5f21365cnxxxfb, r5f21365cdxxxfb r5f21366cnfp, r5f21366cdfp, r5f21366cnfa, r5f21366cdfa, r5f21366cnfb, r5f21366cdfb, r5f21366cnxxxfp, r5f21366cdxxxfp, r5f21366cnxxxfa, r5f21366cdxxxfa, r5f21366cnxxxfb, r5f21366cdxxxfb r5f21367cnfp, r5f21367cdfp, r5f21367cnfa, r5f21367cdfa, r5f21367cnfb, r5f21367cdfb, r5f21367cnxxxfp, r5f21367cdxxxfp, r5f21367cnxxxfa, r5f21367cdxxxfa, r5f21367cnxxxfb, r5f21367cdxxxfb r5f21368cnfp, r5f21368cdfp, r5f21368cnfa, r5f21368cdfa, r5f21368cnfb, r5f21368cdfb, r5f21368cnxxxfp, r5f21368cdxxxfp, r5f21368cnxxxfa, r5f21368cdxxxfa, r5f21368cnxxxfb, r5f21368cdxxxfb r5f2136acnfp, r5f2136 acdfp, r5f2136acnfa, r5f2136acdfa, r5f2136 acnfb, r5f2136acdfb, r5f2136acnxxxfp, r5f2136acdxxxfp, r5f2136acnxxxfa, r5f2136acdxxxfa, r5f2136acnxxxfb, r5f2136acdxxxfb R5F2136CCNFP, r5f2136ccdfp, r5f2136ccnfa, r5f2136ccdfa, r5f2136ccnfb, r5f2136ccdfb, r5f2136ccnxxxfp, r5f2136ccdxxxfp, r5f2136ccnxxxfa, r5f2136ccdxxxfa, r5f2136ccnxxxfb, r5f2136ccdxxxfb 16 kbytes 24 kbytes 32 kbytes 48 kbytes 64 kbytes 96 kbytes 128 kbytes 0c000h 0a000h 08000h 04000h 04000h 04000h 04000h address zzzzzh ? ? ? ? 13fffh 1bfffh 23fffh fffffh 0ffffh 0yyyyh 0xxxxh 00400h 002ffh 00000h internal rom (program rom) internal ram sfr (refer to 4. special function registers (sfrs) ) 02fffh 02c00h sfr (2) (refer to 4. special function registers (sfrs) ) zzzzzh 03fffh 03000h internal rom (data flash) (1) internal rom (program rom) undefined instruction overflow brk instruction address match single step watchdog timer, oscillation stop detection, voltage monitor address break (reserved) reset
r8c/36c group 4. special function registers (sfrs) r01ds0018ej0110 rev.1.10 page 18 of 59 nov 02, 2010 4. special function registers (sfrs) an sfr (special function regist er) is a control register for a peripheral function. tables 4.1 to 4.12 list the special function registers. table 4.13 lists the id code areas and option function select area. table 4.1 sfr information (1) (1) x: undefined notes: 1. the blank areas are reserved and cannot be accessed by users. 2. the cwr bit in the rstfr register is set to 0 after power-on and voltage monitor 0 reset. hardware reset, software reset, or watchdog timer reset does not affect this bit. 3. the csproini bit in the ofs register is set to 0. 4. the lvdas bit in the ofs register is set to 1. 5. the lvdas bit in the ofs register is set to 0. address register symbol after reset 0000h 0001h 0002h 0003h 0004h processor mode register 0 pm0 00h 0005h processor mode register 1 pm1 00h 0006h system clock control register 0 cm0 00101000b 0007h system clock control register 1 cm1 00100000b 0008h module standby control register mstcr 00h 0009h system clock control register 3 cm3 00h 000ah protect register prcr 00h 000bh reset source determination register rstfr 0xxxxxxxb (2) 000ch oscillation stop detection register ocd 00000100b 000dh watchdog timer reset register wdtr xxh 000eh watchdog timer start register wdts xxh 000fh watchdog timer control register wdtc 00111111b 0010h 0011h 0012h 0013h 0014h 0015h high-speed on-chip oscillator control register 7 fra7 when shipping 0016h 0017h 0018h 0019h 001ah 001bh 001ch count source protection mode register cspr 00h 10000000b (3) 001dh 001eh 001fh 0020h 0021h 0022h 0023h high-speed on-chip oscillator control register 0 fra0 00h 0024h high-speed on-chip oscillator control register 1 fra1 when shipping 0025h high-speed on-chip oscillator control register 2 fra2 00h 0026h on-chip reference voltage control register ocvrefcr 00h 0027h 0028h clock prescaler reset flag cpsrf 00h 0029h high-speed on-chip oscillator control register 4 fra4 when shipping 002ah high-speed on-chip oscillator control register 5 fra5 when shipping 002bh high-speed on-chip oscillator control register 6 fra6 when shipping 002ch 002dh 002eh 002fh high-speed on-chip oscillator control register 3 fra3 when shipping 0030h voltage monitor circuit control register cmpa 00h 0031h voltage monitor circuit edge select register vcac 00h 0032h 0033h voltage detect register 1 vca1 00001000b 0034h voltage detect register 2 vca2 00h (4) 00100000b (5) 0035h 0036h voltage detection 1 level select register vd1ls 00000111b 0037h 0038h voltage monitor 0 circuit control register vw0c 1100x010b (4) 1100x011b (5) 0039h voltage monitor 1 circuit control register vw1c 10001010b
r8c/36c group 4. special function registers (sfrs) r01ds0018ej0110 rev.1.10 page 19 of 59 nov 02, 2010 table 4.2 sfr information (2) (1) x: undefined notes: 1. the blank areas are reserved and cannot be accessed by users. 2. selectable by the iicsel bit in the ssuiicsr register. address register symbol after reset 003ah voltage monitor 2 circuit control register vw2c 10000010b 003bh 003ch 003dh 003eh 003fh 0040h 0041h flash memory ready interrupt control register fmrdyic xxxxx000b 0042h 0043h 0044h 0045h 0046h int4 interrupt control register int4ic xx00x000b 0047h timer rc interrupt control register trcic xxxxx000b 0048h timer rd0 interrupt control register trd0ic xxxxx000b 0049h timer rd1 interrupt control register trd1ic xxxxx000b 004ah timer re interrupt control register treic xxxxx000b 004bh uart2 transmit interrupt control register s2tic xxxxx000b 004ch uart2 receive interrupt control register s2ric xxxxx000b 004dh key input interrupt control register kupic xxxxx000b 004eh a/d conversion interrupt control register adic xxxxx000b 004fh ssu interrupt control register/iic bus interrupt control register (2) ssuic/iicic xxxxx000b 0050h timer rf compare 1 interrupt control register cmp1ic xxxxx000b 0051h uart0 transmit interrupt control register s0tic xxxxx000b 0052h uart0 receive interrupt control register s0ric xxxxx000b 0053h uart1 transmit interrupt control register s1tic xxxxx000b 0054h uart1 receive interrupt control register s1ric xxxxx000b 0055h int2 interrupt control register int2ic xx00x000b 0056h timer ra interrupt control register traic xxxxx000b 0057h 0058h timer rb interrupt control register trbic xxxxx000b 0059h int1 interrupt control register int1ic xx00x000b 005ah int3 interrupt control register int3ic xx00x000b 005bh timer rf interrupt control register trfic xxxxx000b 005ch timer rf compare 0 interrupt control register cmp0ic xxxxx000b 005dh int0 interrupt control register int0ic xx00x000b 005eh uart2 bus collision detection interrupt control register u2bcnic xxxxx000b 005fh timer rf capture interrupt control register capic xxxxx000b 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah 006bh timer rg interrupt control register trgic xxxxx000b 006ch 006dh 006eh 006fh 0070h 0071h 0072h voltage monitor 1 interrupt control register vcmp1ic xxxxx000b 0073h voltage monitor 2 interrupt control register vcmp2ic xxxxx000b 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh 007fh
r8c/36c group 4. special function registers (sfrs) r01ds0018ej0110 rev.1.10 page 20 of 59 nov 02, 2010 table 4.3 sfr information (3) (1) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 0080h dtc activation control register dtctl 00h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h dtc activation enable register 0 dtcen0 00h 0089h dtc activation enable register 1 dtcen1 00h 008ah dtc activation enable register 2 dtcen2 00h 008bh dtc activation enable register 3 dtcen3 00h 008ch dtc activation enable register 4 dtcen4 00h 008dh dtc activation enable register 5 dtcen5 00h 008eh dtc activation enable register 6 dtcen6 00h 008fh 0090h timer rf register trf 00h 00h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009ah timer rf control register 0 trfcr0 00h 009bh timer rf control register 1 trfcr1 00h 009ch capture and compare 0 register trfm0 00h 00h 009dh 009eh compare 1 register trfm1 ffh ffh 009fh 00a0h uart0 transmit/receive mode register u0mr 00h 00a1h uart0 bit rate register u0brg xxh 00a2h uart0 transmit buffer register u0tb xxh xxh 00a3h 00a4h uart0 transmit/receive control register 0 u0c0 00001000b 00a5h uart0 transmit/receive control register 1 u0c1 00000010b 00a6h uart0 receive buffer register u0rb xxh xxh 00a7h 00a8h uart2 transmit/receive mode register u2mr 00h 00a9h uart2 bit rate register u2brg xxh 00aah uart2 transmit buffer register u2tb xxh xxh 00abh 00ach uart2 transmit/receive control register 0 u2c0 00001000b 00adh uart2 transmit/receive control register 1 u2c1 00000010b 00aeh uart2 receive buffer register u2rb xxh xxh 00afh 00b0h uart2 digital filter function select register urxdf 00h 00b1h 00b2h 00b3h 00b4h 00b5h 00b6h 00b7h 00b8h 00b9h 00bah 00bbh uart2 special mode register 5 u2smr5 00h 00bch uart2 special mode register 4 u2smr4 00h 00bdh uart2 special mode register 3 u2smr3 000x0x0xb 00beh uart2 special mode register 2 u2smr2 x0000000b 00bfh uart2 special mode register u2smr x0000000b
r8c/36c group 4. special function registers (sfrs) r01ds0018ej0110 rev.1.10 page 21 of 59 nov 02, 2010 table 4.4 sfr information (4) (1) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 00c0h a/d register 0 ad0 xxh 000000xxb 00c1h 00c2h a/d register 1 ad1 xxh 000000xxb 00c3h 00c4h a/d register 2 ad2 xxh 000000xxb 00c5h 00c6h a/d register 3 ad3 xxh 000000xxb 00c7h 00c8h a/d register 4 ad4 xxh 000000xxb 00c9h 00cah a/d register 5 ad5 xxh 000000xxb 00cbh 00cch a/d register 6 ad6 xxh 000000xxb 00cdh 00ceh a/d register 7 ad7 xxh 000000xxb 00cfh 00d0h 00d1h 00d2h 00d3h 00d4h a/d mode register admod 00h 00d5h a/d input select register adinsel 11000000b 00d6h a/d control register 0 adcon0 00h 00d7h a/d control register 1 adcon1 00h 00d8h d/a0 register da0 00h 00d9h d/a1 register da1 00h 00dah 00dbh 00dch d/a control register dacon 00h 00ddh 00deh 00dfh 00e0h port p0 register p0 xxh 00e1h port p1 register p1 xxh 00e2h port p0 direction register pd0 00h 00e3h port p1 direction register pd1 00h 00e4h port p2 register p2 xxh 00e5h port p3 register p3 xxh 00e6h port p2 direction register pd2 00h 00e7h port p3 direction register pd3 00h 00e8h port p4 register p4 xxh 00e9h port p5 register p5 xxh 00eah port p4 direction register pd4 00h 00ebh port p5 direction register pd5 00h 00ech port p6 register p6 xxh 00edh 00eeh port p6 direction register pd6 00h 00efh 00f0h port p8 register p8 xxh 00f1h 00f2h port p8 direction register pd8 00h 00f3h 00f4h 00f5h 00f6h 00f7h 00f8h 00f9h 00fah 00fbh 00fch 00fdh 00feh 00ffh
r8c/36c group 4. special function registers (sfrs) r01ds0018ej0110 rev.1.10 page 22 of 59 nov 02, 2010 table 4.5 sfr information (5) (1) note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 0100h timer ra control register tracr 00h 0101h timer ra i/o control register traioc 00h 0102h timer ra mode register tramr 00h 0103h timer ra prescaler register trapre ffh 0104h timer ra register tra ffh 0105h lin control register 2 lincr2 00h 0106h lin control register lincr 00h 0107h lin status register linst 00h 0108h timer rb control register trbcr 00h 0109h timer rb one-shot control register trbocr 00h 010ah timer rb i/o control register trbioc 00h 010bh timer rb mode register trbmr 00h 010ch timer rb prescaler register trbpre ffh 010dh timer rb secondary register trbsc ffh 010eh timer rb primary register trbpr ffh 010fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h timer re second data register / counter data register tresec 00h 0119h timer re minute data register / compare data register tremin 00h 011ah timer re hour data register trehr 00h 011bh timer re day of week data register trewk 00h 011ch timer re control register 1 trecr1 00h 011dh timer re control register 2 trecr2 00h 011eh timer re count source select register trecsr 00001000b 011fh 0120h timer rc mode register trcmr 01001000b 0121h timer rc control register 1 trccr1 00h 0122h timer rc interrupt enable register trcier 01110000b 0123h timer rc status register trcsr 01110000b 0124h timer rc i/o control register 0 trcior0 10001000b 0125h timer rc i/o control register 1 trcior1 10001000b 0126h timer rc counter trc 00h 00h 0127h 0128h timer rc general register a trcgra ffh ffh 0129h 012ah timer rc general register b trcgrb ffh ffh 012bh 012ch timer rc general register c trcgrc ffh ffh 012dh 012eh timer rc general register d trcgrd ffh ffh 012fh 0130h timer rc control register 2 trccr2 00011000b 0131h timer rc digital filter function select register trcdf 00h 0132h timer rc output master enable register trcoer 01111111b 0133h timer rc trigger control register trcadcr 00h 0134h 0135h timer rd control expansion register trdecr 00h 0136h timer rd trigger control register trdadcr 00h 0137h timer rd start register trdstr 11111100b 0138h timer rd mode register trdmr 00001110b 0139h timer rd pwm mode register trdpmr 10001000b 013ah timer rd function control register trdfcr 10000000b 013bh timer rd output master enable register 1 trdoer1 ffh 013ch timer rd output master enable register 2 trdoer2 01111111b 013dh timer rd output control register trdocr 00h 013eh timer rd digital filter function select register 0 trddf0 00h 013fh timer rd digital filter function select register 1 trddf1 00h
r8c/36c group 4. special function registers (sfrs) r01ds0018ej0110 rev.1.10 page 23 of 59 nov 02, 2010 table 4.6 sfr information (6) (1) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 0140h timer rd control register 0 trdcr0 00h 0141h timer rd i/o control register a0 trdiora0 10001000b 0142h timer rd i/o control register c0 trdiorc0 10001000b 0143h timer rd status register 0 trdsr0 11100000b 0144h timer rd interrupt enable register 0 trdier0 11100000b 0145h timer rd pwm mode output level control register 0 trdpocr0 11111000b 0146h timer rd counter 0 trd0 00h 00h 0147h 0148h timer rd general register a0 trdgra0 ffh ffh 0149h 014ah timer rd general register b0 trdgrb0 ffh ffh 014bh 014ch timer rd general register c0 trdgrc0 ffh ffh 014dh 014eh timer rd general register d0 trdgrd0 ffh ffh 014fh 0150h timer rd control register 1 trdcr1 00h 0151h timer rd i/o control register a1 trdiora1 10001000b 0152h timer rd i/o control register c1 trdiorc1 10001000b 0153h timer rd status register 1 trdsr1 11000000b 0154h timer rd interrupt enable register 1 trdier1 11100000b 0155h timer rd pwm mode output level control register 1 trdpocr1 11111000b 0156h timer rd counter 1 trd1 00h 00h 0157h 0158h timer rd general register a1 trdgra1 ffh ffh 0159h 015ah timer rd general register b1 trdgrb1 ffh ffh 015bh 015ch timer rd general register c1 trdgrc1 ffh ffh 015dh 015eh timer rd general register d1 trdgrd1 ffh ffh 015fh 0160h uart1 transmit/receive mode register u1mr 00h 0161h uart1 bit rate register u1brg xxh 0162h uart1 transmit buffer register u1tb xxh xxh 0163h 0164h uart1 transmit/receive control register 0 u1c0 00001000b 0165h uart1 transmit/receive control register 1 u1c1 00000010b 0166h uart1 receive buffer register u1rb xxh xxh 0167h 0168h 0169h 016ah 016bh 016ch 016dh 016eh 016fh 0170h timer rg mode register trgmr 01000000b 0171h timer rg count control register trgcntc 00h 0172h timer rg control register trgcr 10000000b 0173h timer rg interrupt enable register trgier 11110000b 0174h timer rg status register trgsr 11100000b 0175h timer rg i/o control register trgior 00h 0176h timer rg counter trg 00h 00h 0177h 0178h timer rg general register a trggra ffh ffh 0179h 017ah timer rg general register b trggrb ffh ffh 017bh 017ch timer rg general register c trggrc ffh ffh 017dh 017eh timer rg general register d trggrd ffh ffh 017fh
r8c/36c group 4. special function registers (sfrs) r01ds0018ej0110 rev.1.10 page 24 of 59 nov 02, 2010 table 4.7 sfr information (7) (1) x: undefined notes: 1. the blank areas are reserved and cannot be accessed by users. 2. selectable by the iicsel bit in the ssuiicsr register. address register symbol after reset 0180h timer ra pin select register trasr 00h 0181h timer rb/rc pin select register trbrcsr 00h 0182h timer rc pin select register 0 trcpsr0 00h 0183h timer rc pin select register 1 trcpsr1 00h 0184h timer rd pin select register 0 trdpsr0 00h 0185h timer rd pin select register 1 trdpsr1 00h 0186h timer pin select register timsr 00h 0187h timer rf output control register trfout 00h 0188h uart0 pin select register u0sr 00h 0189h uart1 pin select register u1sr 00h 018ah uart2 pin select register 0 u2sr0 00h 018bh uart2 pin select register 1 u2sr1 00h 018ch ssu/iic pin select register ssuiicsr 00h 018dh 018eh int interrupt input pin select register intsr 00h 018fh i/o function pin select register pinsr 00h 0190h 0191h 0192h 0193h ss bit counter register ssbr 11111000b 0194h ss transmit data register l / iic bus transmit data register (2) sstdr / icdrt ffh 0195h ss transmit data register h (2) sstdrh ffh 0196h ss receive data register l / iic bus receive data register (2) ssrdr / icdrr ffh 0197h ss receive data register h (2) ssrdrh ffh 0198h ss control register h / iic bus control register 1 (2) sscrh / iccr1 00h 0199h ss control register l / iic bus control register 2 (2) sscrl / iccr2 01111101b 019ah ss mode register / iic bus mode register (2) ssmr / icmr 00010000b / 00011000b 019bh ss enable register / iic bus interrupt enable register (2) sser / icier 00h 019ch ss status register / iic bus status register (2) sssr / icsr 00h / 0000x000b 019dh ss mode register 2 / slave address register (2) ssmr2 / sar 00h 019eh 019fh 01a0h 01a1h 01a2h 01a3h 01a4h 01a5h 01a6h 01a7h 01a8h 01a9h 01aah 01abh 01ach 01adh 01aeh 01afh 01b0h 01b1h 01b2h flash memory status register fst 10000x00b 01b3h 01b4h flash memory control register 0 fmr0 00h 01b5h flash memory control register 1 fmr1 00h 01b6h flash memory control register 2 fmr2 00h 01b7h 01b8h 01b9h 01bah 01bbh 01bch 01bdh 01beh 01bfh
r8c/36c group 4. special function registers (sfrs) r01ds0018ej0110 rev.1.10 page 25 of 59 nov 02, 2010 table 4.8 sfr information (8) (1) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 01c0h address match interrupt register 0 rmad0 xxh xxh 0000xxxxb 01c1h 01c2h 01c3h address match interrupt enable register 0 aier0 00h 01c4h address match interrupt register 1 rmad1 xxh xxh 0000xxxxb 01c5h 01c6h 01c7h address match interrupt enable register 1 aier1 00h 01c8h 01c9h 01cah 01cbh 01cch 01cdh 01ceh 01cfh 01d0h 01d1h 01d2h 01d3h 01d4h 01d5h 01d6h 01d7h 01d8h 01d9h 01dah 01dbh 01dch 01ddh 01deh 01dfh 01e0h pull-up control register 0 pur0 00h 01e1h pull-up control register 1 pur1 00h 01e2h pull-up control register 2 pur2 00h 01e3h 01e4h 01e5h 01e6h 01e7h 01e8h 01e9h 01eah 01ebh 01ech 01edh 01eeh 01efh 01f0h port p1 drive capacity control register p1drr 00h 01f1h port p2 drive capacity control register p2drr 00h 01f2h drive capacity control register 0 drr0 00h 01f3h drive capacity control register 1 drr1 00h 01f4h drive capacity control register 2 drr2 00h 01f5h input threshold control register 0 vlt0 00h 01f6h input threshold control register 1 vlt1 00h 01f7h input threshold control register 2 vlt2 00h 01f8h comparator b control register 0 intcmp 00h 01f9h 01fah external input enable register 0 inten 00h 01fbh external input enable register 1 inten1 00h 01fch int input filter select register 0 intf 00h 01fdh int input filter select register 1 intf1 00h 01feh key input enable register 0 kien 00h 01ffh
r8c/36c group 4. special function registers (sfrs) r01ds0018ej0110 rev.1.10 page 26 of 59 nov 02, 2010 table 4.9 sfr information (9) (1) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 2c00h dtc transfer vector area xxh 2c01h dtc transfer vector area xxh 2c02h dtc transfer vector area xxh 2c03h dtc transfer vector area xxh 2c04h dtc transfer vector area xxh 2c05h dtc transfer vector area xxh 2c06h dtc transfer vector area xxh 2c07h dtc transfer vector area xxh 2c08h dtc transfer vector area xxh 2c09h dtc transfer vector area xxh 2c0ah dtc transfer vector area xxh : dtc transfer vector area xxh : dtc transfer vector area xxh 2c3ah dtc transfer vector area xxh 2c3bh dtc transfer vector area xxh 2c3ch dtc transfer vector area xxh 2c3dh dtc transfer vector area xxh 2c3eh dtc transfer vector area xxh 2c3fh dtc transfer vector area xxh 2c40h dtc control data 0 dtcd0 xxh 2c41h xxh 2c42h xxh 2c43h xxh 2c44h xxh 2c45h xxh 2c46h xxh 2c47h xxh 2c48h dtc control data 1 dtcd1 xxh 2c49h xxh 2c4ah xxh 2c4bh xxh 2c4ch xxh 2c4dh xxh 2c4eh xxh 2c4fh xxh 2c50h dtc control data 2 dtcd2 xxh 2c51h xxh 2c52h xxh 2c53h xxh 2c54h xxh 2c55h xxh 2c56h xxh 2c57h xxh 2c58h dtc control data 3 dtcd3 xxh 2c59h xxh 2c5ah xxh 2c5bh xxh 2c5ch xxh 2c5dh xxh 2c5eh xxh 2c5fh xxh 2c60h dtc control data 4 dtcd4 xxh 2c61h xxh 2c62h xxh 2c63h xxh 2c64h xxh 2c65h xxh 2c66h xxh 2c67h xxh 2c68h dtc control data 5 dtcd5 xxh 2c69h xxh 2c6ah xxh 2c6bh xxh 2c6ch xxh 2c6dh xxh 2c6eh xxh 2c6fh xxh
r8c/36c group 4. special function registers (sfrs) r01ds0018ej0110 rev.1.10 page 27 of 59 nov 02, 2010 table 4.10 sfr information (10) (1) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 2c70h dtc control data 6 dtcd6 xxh 2c71h xxh 2c72h xxh 2c73h xxh 2c74h xxh 2c75h xxh 2c76h xxh 2c77h xxh 2c78h dtc control data 7 dtcd7 xxh 2c79h xxh 2c7ah xxh 2c7bh xxh 2c7ch xxh 2c7dh xxh 2c7eh xxh 2c7fh xxh 2c80h dtc control data 8 dtcd8 xxh 2c81h xxh 2c82h xxh 2c83h xxh 2c84h xxh 2c85h xxh 2c86h xxh 2c87h xxh 2c88h dtc control data 9 dtcd9 xxh 2c89h xxh 2c8ah xxh 2c8bh xxh 2c8ch xxh 2c8dh xxh 2c8eh xxh 2c8fh xxh 2c90h dtc control data 10 dtcd10 xxh 2c91h xxh 2c92h xxh 2c93h xxh 2c94h xxh 2c95h xxh 2c96h xxh 2c97h xxh 2c98h dtc control data 11 dtcd11 xxh 2c99h xxh 2c9ah xxh 2c9bh xxh 2c9ch xxh 2c9dh xxh 2c9eh xxh 2c9fh xxh 2ca0h dtc control data 12 dtcd12 xxh 2ca1h xxh 2ca2h xxh 2ca3h xxh 2ca4h xxh 2ca5h xxh 2ca6h xxh 2ca7h xxh 2ca8h dtc control data 13 dtcd13 xxh 2ca9h xxh 2caah xxh 2cabh xxh 2cach xxh 2cadh xxh 2caeh xxh 2cafh xxh
r8c/36c group 4. special function registers (sfrs) r01ds0018ej0110 rev.1.10 page 28 of 59 nov 02, 2010 table 4.11 sfr information (11) (1) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 2cb0h dtc control data 14 dtcd14 xxh 2cb1h xxh 2cb2h xxh 2cb3h xxh 2cb4h xxh 2cb5h xxh 2cb6h xxh 2cb7h xxh 2cb8h dtc control data 15 dtcd15 xxh 2cb9h xxh 2cbah xxh 2cbbh xxh 2cbch xxh 2cbdh xxh 2cbeh xxh 2cbfh xxh 2cc0h dtc control data 16 dtcd16 xxh 2cc1h xxh 2cc2h xxh 2cc3h xxh 2cc4h xxh 2cc5h xxh 2cc6h xxh 2cc7h xxh 2cc8h dtc control data 17 dtcd17 xxh 2cc9h xxh 2ccah xxh 2ccbh xxh 2ccch xxh 2ccdh xxh 2cceh xxh 2ccfh xxh 2cd0h dtc control data 18 dtcd18 xxh 2cd1h xxh 2cd2h xxh 2cd3h xxh 2cd4h xxh 2cd5h xxh 2cd6h xxh 2cd7h xxh 2cd8h dtc control data 19 dtcd19 xxh 2cd9h xxh 2cdah xxh 2cdbh xxh 2cdch xxh 2cddh xxh 2cdeh xxh 2cdfh xxh 2ce0h dtc control data 20 dtcd20 xxh 2ce1h xxh 2ce2h xxh 2ce3h xxh 2ce4h xxh 2ce5h xxh 2ce6h xxh 2ce7h xxh 2ce8h dtc control data 21 dtcd21 xxh 2ce9h xxh 2ceah xxh 2cebh xxh 2cech xxh 2cedh xxh 2ceeh xxh 2cefh xxh
r8c/36c group 4. special function registers (sfrs) r01ds0018ej0110 rev.1.10 page 29 of 59 nov 02, 2010 table 4.12 sfr information (12) (1) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. table 4.13 id code areas and option function select area notes: 1. the option function select area is allocated in the flash me mory, not in the sfrs. set appropriate values as rom data by a pr ogram. do not write additions to the option function select area. if the block including the option function select area is erased, th e option function select area is set to ffh. when blank products are shipped, the option function select area is set to ffh. it is set to the written value after written by the user. when factory-programming products are shipped, the value of the option function select area is the value programmed by the user . 2. the id code areas are allocated in the flash memory, not in the sfrs. set appropriate values as rom data by a program. do not write additions to the id code areas. if the block includ ing the id code areas is erased, the id code areas are set to f fh. when blank products are shipped, the id code areas are set to ffh. they are set to the written value after written by the user. when factory-programming products are shipped, the value of the id code areas is the va lue programmed by the user. address register symbol after reset 2cf0h dtc control data 22 dtcd22 xxh 2cf1h xxh 2cf2h xxh 2cf3h xxh 2cf4h xxh 2cf5h xxh 2cf6h xxh 2cf7h xxh 2cf8h dtc control data 23 dtcd23 xxh 2cf9h xxh 2cfah xxh 2cfbh xxh 2cfch xxh 2cfdh xxh 2cfeh xxh 2cffh xxh 2d00h : 2fffh address area name symbol after reset : ffdbh option function select register 2 ofs2 (note 1) : ffdfh id1 (note 2) : ffe3h id2 (note 2) : ffebh id3 (note 2) : ffefh id4 (note 2) : fff3h id5 (note 2) : fff7h id6 (note 2) : fffbh id7 (note 2) : ffffh option function select register ofs (note 1)
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 30 of 59 nov 02, 2010 5. electrical characteristics table 5.1 absolute maximum ratings symbol parameter condition rated value unit v cc /av cc supply voltage ? 0.3 to 6.5 v v i input voltage ? 0.3 to v cc + 0.3 v v o output voltage ? 0.3 to v cc + 0.3 v p d power dissipation ? 40 c t opr 85 c500mw t opr operating ambient temperature ? 20 to 85 (n version)/ ? 40 to 85 (d version) c t stg storage temperature ? 65 to 150 c
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 31 of 59 nov 02, 2010 notes: 1. v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified. 2. the average output current indicates the average value of current measured during 100 ms. 3. foco40m can be used as the count source for timer rc, timer rd or timer rg in the range of v cc = 2.7 to 5.5 v. table 5.2 recommended operating conditions (1) symbol parameter conditions standard unit min. typ. max. v cc /av cc supply voltage 1.8 ? 5.5 v v ss /av ss supply voltage ? 0 ? v v ih input ?h? voltage other than cmos input 0.8 v cc ?v cc v cmos input input level switching function (i/o port) input level selection: 0.35 v cc 4.0 v v cc 5.5 v 0.5 v cc ?v cc v 2.7 v v cc < 4.0 v 0.55 v cc ?v cc v 1.8 v v cc < 2.7 v 0.65 v cc ?v cc v input level selection: 0.5 v cc 4.0 v v cc 5.5 v 0.65 v cc ?v cc v 2.7 v v cc < 4.0 v 0.7 v cc ?v cc v 1.8 v v cc < 2.7 v 0.8 v cc ?v cc v input level selection: 0.7 v cc 4.0 v v cc 5.5 v 0.85 v cc ?v cc v 2.7 v v cc < 4.0 v 0.85 v cc ?v cc v 1.8 v v cc < 2.7 v 0.85 v cc ?v cc v external clock input (xout) 1.2 ? v cc v v il input ?l? voltage other than cmos input 0 ? 0.2 v cc v cmos input input level switching function (i/o port) input level selection: 0.35 v cc 4.0 v v cc 5.5 v 0 ? 0.2 v cc v 2.7 v v cc < 4.0 v 0 ? 0.2 v cc v 1.8 v v cc < 2.7 v 0 ? 0.2 v cc v input level selection: 0.5 v cc 4.0 v v cc 5.5 v 0 ? 0.4 v cc v 2.7 v v cc < 4.0 v 0 ? 0.3 v cc v 1.8 v v cc < 2.7 v 0 ? 0.2 v cc v input level selection: 0.7 v cc 4.0 v v cc 5.5 v 0 ? 0.55 v cc v 2.7 v v cc < 4.0 v 0 ? 0.45 v cc v 1.8 v v cc < 2.7 v 0 ? 0.35 v cc v external clock input (xout) 0 ? 0.4 v i oh(sum) peak sum output ?h? current sum of all pins i oh(peak) ?? ? 160 ma i oh(sum) average sum output ?h? current sum of all pins i oh(avg) ?? ? 80 ma i oh(peak) peak output ?h? current drive capacity low ? ? ? 10 ma drive capacity high ? ? ? 40 ma i oh(avg) average output ?h? current drive capacity low ? ? ? 5ma drive capacity high ? ? ? 20 ma i ol(sum) peak sum output ?l? current sum of all pins i ol(peak) ? ? 160 ma i ol(sum) average sum output ?l? current sum of all pins i ol(avg) ??80ma i ol(peak) peak output ?l? current drive capacity low ? ? 10 ma drive capacity high ? ? 40 ma i ol(avg) average output ?l? current drive capacity low ? ? 5 ma drive capacity high ? ? 20 ma f (xin) xin clock input oscillation frequency 2.7 v v cc 5.5 v ? ? 20 mhz 1.8 v v cc < 2.7 v ? ? 5 mhz f (xcin) xcin clock input oscillation frequency 1.8 v v cc 5.5 v ? 32.768 50 khz foco40m when used as the count source for timer rc, timer rd or timer rg (3) 2.7 v v cc 5.5 v 32 ? 40 mhz foco-f foco-f frequency 2.7 v v cc 5.5 v ? ? 20 mhz 1.8 v v cc < 2.7 v ? ? 5 mhz ? system clock frequency 2.7 v v cc 5.5 v ? ? 20 mhz 1.8 v v cc < 2.7 v ? ? 5 mhz f (bclk) cpu clock frequency 2.7 v v cc 5.5 v ? ? 20 mhz 1.8 v v cc < 2.7 v ? ? 5 mhz
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 32 of 59 nov 02, 2010 figure 5.1 ports p0 to p6, p8 timing measurement circuit p0 p1 p2 p3 p4 p5 p6 p8 30 pf
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 33 of 59 nov 02, 2010 notes: 1. v cc /av cc = v ref = 2.2 to 5.5 v, v ss = 0 v, and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified. 2. the a/d conversion result will be undefined in wait mode, st op mode, when the flash memory stops, and in low-current- consumption mode. do not perform a/d conversion in these st ates or transition to these states during a/d conversion. 3. when the analog input voltage is over the reference voltage, th e a/d conversion result will be 3ffh in 10-bit mode and ffh in 8-bit mode. table 5.3 a/d converter characteristics symbol parameter conditions standard unit min. typ. max. ? resolution v ref = av cc ??10bit ? absolute accuracy 10-bit mode v ref = av cc = 5.0 v an0 to an7 input, an8 to an11 input ? ? 3 lsb v ref = av cc = 3.3 v an0 to an7 input, an8 to an11 input ? ? 5 lsb v ref = av cc = 3.0 v an0 to an7 input, an8 to an11 input ? ? 5 lsb v ref = av cc = 2.2 v an0 to an7 input, an8 to an11 input ? ? 5 lsb 8-bit mode v ref = av cc = 5.0 v an0 to an7 input, an8 to an11 input ? ? 2 lsb v ref = av cc = 3.3 v an0 to an7 input, an8 to an11 input ? ? 2 lsb v ref = av cc = 3.0 v an0 to an7 input, an8 to an11 input ? ? 2 lsb v ref = av cc = 2.2 v an0 to an7 input, an8 to an11 input ? ? 2 lsb ad a/d conversion clock 4.0 v v ref = av cc 5.5 v (2) 2?20mhz 3.2 v v ref = av cc 5.5 v (2) 2?16mhz 2.7 v v ref = av cc 5.5 v (2) 2?10mhz 2.2 v v ref = av cc 5.5 v (2) 2?5mhz ? tolerance level impedance ? 3 ? k ? t conv conversion time 10-bit mode v ref = av cc = 5.0 v, ad = 20 mhz 2.2 ? ? s 8-bit mode v ref = av cc = 5.0 v, ad = 20 mhz 2.2 ? ? s t samp sampling time ad = 20 mhz 0.8 ? ? s i vref v ref current v cc = 5.0 v, xin = f1 = ad = 20 mhz ? 45 ? a v ref reference voltage 2.2 ? av cc v v ia analog input voltage (3) 0?v ref v ocvref on-chip reference voltage 2 mhz ad 4 mhz 1.19 1.34 1.49 v
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 34 of 59 nov 02, 2010 notes: 1. v cc /av cc = v ref = 2.7 to 5.5 v and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified. 2. this applies when one d/a converter is used and the value of the dai register (i = 0 or 1) for the unused d/a converter is 00 h. the resistor ladder of the a/ d converter is not included. notes: 1. v cc = 2.7 to 5.5 v and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified. 2. when the digital filter is disabled. table 5.4 d/a converter characteristics symbol parameter condition standard unit min. typ. max. ? resolution ?? 8bit ? absolute accuracy ? ? 2.5 lsb t su setup time ?? 3 s r o output resistor ?6?k ? i vref reference power input current (note 2) ? ? 1.5 ma table 5.5 comparator b electrical characteristics symbol parameter condition standard unit min. typ. max. v ref ivref1, ivref3 input reference voltage 0 ? v cc ? 1.4 v v i ivcmp1, ivcmp3 input voltage ? 0.3 ? v cc + 0.3 v ? offset ? 5 100 mv t d comparator output delay time (2) v i = v ref 100 mv ? 0.1 ? s i cmp comparator operating current v cc = 5.0 v ? 17.5 ? a
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 35 of 59 nov 02, 2010 notes: 1. v cc = 2.7 to 5.5 v and t opr = 0 to 60 c, unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 1,000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to different addresses in block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. endurance to guarantee all electrical characteristics after progr am and erase. (1 to min. value can be guaranteed.) 4. in a system that executes multiple programming operations, t he actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possibl e is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. it is also advisable to retain data on t he erasure endurance of each block and limit the number of erase operations to a certain number. 5. if an error occurs during block erase, attempt to execute th e clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 7. the data hold time includes time that the power supply is off or the clock is not supplied. table 5.6 flash memory (program rom) electrical characteristics symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) 1,000 (3) ??times ? byte program time ? 80 500 s ? block erase time ? 0.3 ? s t d(sr-sus) time delay from suspend request until suspend ? ? 5 + cpu clock 3 cycles ms ? interval from erase start/restart until following suspend request 0? ? s ? time from suspend until erase restart ? ? 30 + cpu clock 1 cycle s t d(cmdrst -ready) time from when command is forcibly stopped until reading is enabled ? ? 30 + cpu clock 1 cycle s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 1.8 ? 5.5 v ? program, erase temperature 0 ? 60 c ? data hold time (7) ambient temperature = 55 c20 ? ? year
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 36 of 59 nov 02, 2010 notes: 1. v cc = 2.7 to 5.5 v and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 10,000), each bl ock can be erased n times. fo r example, if 1,024 1-byte writes are performed to different addresses in block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. endurance to guarantee all electrical characteristics after progr am and erase. (1 to min. value can be guaranteed.) 4. in a system that executes multiple programming operations, t he actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possibl e is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. in addition, av eraging the erasure endurance between blocks a to d can further reduce the actual erasure endurance. it is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 5. if an error occurs during block erase, attempt to execute th e clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 7. ? 40 c for d version. 8. the data hold time includes time that the pow er supply is off or t he clock is not supplied. figure 5.2 time delay until suspend table 5.7 flash memory (data flash block a to block d) electric al characteristics symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) 10,000 (3) ??times ? byte program time (program/erase endurance 1,000 times) ? 160 1500 s ? byte program time (program/erase endurance > 1,000 times) ? 300 1500 s ? block erase time (program/erase endurance 1,000 times) ?0.2 1 s ? block erase time (program/erase endurance > 1,000 times) ?0.3 1 s t d(sr-sus) time delay from suspend request until suspend ? ? 5 + cpu clock 3 cycles ms ? interval from erase start/restart until following suspend request 0? ? s ? time from suspend until erase restart ? ? 30 + cpu clock 1 cycle s t d(cmdrst -ready) time from when command is forcibly stopped until reading is enabled ? ? 30 + cpu clock 1 cycle s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 1.8 ? 5.5 v ? program, erase temperature ? 20 (7) ?85 c ? data hold time (8) ambient temperature = 55 c20 ? ? year fst6 bit suspend request (fmr21 bit) fixed time t d(sr-sus) clock-dependent time access restart fst6, fst7: bit in fst register fmr21: bit in fmr2 register fst7 bit
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 37 of 59 nov 02, 2010 notes: 1. the measurement condition is v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version). 2. select the voltage detection level with bits vdsel0 and vdsel1 in the ofs register. 3. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca25 bit in the vca2 register to 0. 4. time until the voltage monitor 0 reset is generated after the voltage passes v det0 . notes: 1. the measurement condition is v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version). 2. select the voltage detection level with bits vd1s0 to vd1s3 in the vd1ls register. 3. time until the voltage monitor 1 interrupt request is generated after the voltage passes v det1 . 4. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca26 bit in the vca2 register to 0. table 5.8 voltage detection 0 circ uit electrical characteristics symbol parameter condition standard unit min. typ. max. v det0 voltage detection level vdet0_0 (2) 1.80 1.90 2.05 v voltage detection level vdet0_1 (2) 2.15 2.35 2.50 v voltage detection level vdet0_2 (2) 2.70 2.85 3.05 v voltage detection level vdet0_3 (2) 3.55 3.80 4.05 v ? voltage detection 0 circuit response time (4) at the falling of v cc from 5.0 v to (vdet0_0 ? 0.1) v ? 6 150 s ? voltage detection circuit self power consumption vca25 = 1, v cc = 5.0 v ? 1.5 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ? ? 100 s table 5.9 voltage detection 1 circ uit electrical characteristics symbol parameter condition standard unit min. typ. max. v det1 voltage detection level vdet1_0 (2) at the falling of v cc 2.00 2.20 2.40 v voltage detection level vdet1_1 (2) at the falling of v cc 2.15 2.35 2.55 v voltage detection level vdet1_2 (2) at the falling of v cc 2.30 2.50 2.70 v voltage detection level vdet1_3 (2) at the falling of v cc 2.45 2.65 2.85 v voltage detection level vdet1_4 (2) at the falling of v cc 2.60 2.80 3.00 v voltage detection level vdet1_5 (2) at the falling of v cc 2.75 2.95 3.15 v voltage detection level vdet1_6 (2) at the falling of v cc 2.85 3.10 3.40 v voltage detection level vdet1_7 (2) at the falling of v cc 3.00 3.25 3.55 v voltage detection level vdet1_8 (2) at the falling of v cc 3.15 3.40 3.70 v voltage detection level vdet1_9 (2) at the falling of v cc 3.30 3.55 3.85 v voltage detection level vdet1_a (2) at the falling of v cc 3.45 3.70 4.00 v voltage detection level vdet1_b (2) at the falling of v cc 3.60 3.85 4.15 v voltage detection level vdet1_c (2) at the falling of v cc 3.75 4.00 4.30 v voltage detection level vdet1_d (2) at the falling of v cc 3.90 4.15 4.45 v voltage detection level vdet1_e (2) at the falling of v cc 4.05 4.30 4.60 v voltage detection level vdet1_f (2) at the falling of v cc 4.20 4.45 4.75 v ? hysteresis width at the rising of v cc in voltage detection 1 circuit vdet1_0 to vdet1_5 selected ?0.07? v vdet1_6 to vdet1_f selected ?0.10? v ? voltage detection 1 circuit response time (3) at the falling of v cc from 5.0 v to (vdet1_0 ? 0.1) v ? 60 150 s ? voltage detection circuit self power consumption vca26 = 1, v cc = 5.0 v ? 1.7 ? a t d(e-a) waiting time until voltage detection circuit operation starts (4) ? ? 100 s
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 38 of 59 nov 02, 2010 notes: 1. the measurement condition is v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version). 2. time until the voltage monitor 2 interrupt request is generated after the voltage passes v det2 . 3. necessary time until the voltage detection circuit operates a fter setting to 1 again after setting the vca27 bit in the vca2 register to 0. notes: 1. the measurement condition is t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified. 2. to use the power-on reset function, enable voltage monitor 0 reset by setting the lvdas bit in the ofs register to 0. figure 5.3 power-on reset circuit electrical characteristics table 5.10 voltage detection 2 circ uit electrical characteristics symbol parameter condition standard unit min. typ. max. v det2 voltage detection level vdet2_0 at the falling of v cc 3.70 4.00 4.30 v ? hysteresis width at the rising of v cc in voltage detection 2 circuit ?0.10? v ? voltage detection 2 circuit response time (2) at the falling of v cc from 5.0 v to (vdet2_0 ? 0.1) v ? 20 150 s ? voltage detection circuit self power consumption vca27 = 1, v cc = 5.0 v ? 1.7 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ? ? 100 s table 5.11 power-on reset circuit (2) symbol parameter condition standard unit min. typ. max. t rth external power v cc rise gradient (1) 0 ? 50,000 mv/msec notes: 1. v det0 indicates the voltage detection level of the voltage detection 0 circuit. refer to 6. voltage detection circuit of user?s manual: hardware (r01uh0095ej0110) for details. 2. t w(por) indicates the duration the external power v cc must be held below the valid voltage (0.5 v) to enable a power-on reset. when turning on the power after it falls with voltage monitor 0 reset disabled, maintain t w(por) for 1 ms or more. v det0 (1) 0.5 v internal reset signal t w(por) (2) voltage detection 0 circuit response time v det0 (1) external power v cc t rth t rth 1 f oco-s 32 1 f oco-s 32
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 39 of 59 nov 02, 2010 notes: 1. v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified. 2. this enables the setting errors of bit rates such as 9600 bp s and 38400 bps to be 0% when the serial interface is used in uart mode. note: 1. v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified. notes: 1. the measurement condition is v cc = 1.8 to 5.5 v and t opr = 25 c. 2. waiting time until the internal power supp ly generation circuit stab ilizes during power-on. table 5.12 high-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. ? high-speed on-chip oscillator frequency after reset v cc = 1.8 v to 5.5 v ? 20 c t opr 85 c 38.4 40 41.6 mhz v cc = 1.8 v to 5.5 v ? 40 c t opr 85 c 38.0 40 42.0 mhz high-speed on-chip oscillator frequency when the fra4 register correction value is written into the fra1 register and the fra5 register correction value into the fra3 register (2) v cc = 1.8 v to 5.5 v ? 20 c t opr 85 c 35.389 36.864 38.338 mhz v cc = 1.8 v to 5.5 v ? 40 c t opr 85 c 35.020 36.864 38.707 mhz high-speed on-chip oscillator frequency when the fra6 register correction value is written into the fra1 register and the fra7 register correction value into the fra3 register v cc = 1.8 v to 5.5 v ? 20 c t opr 85 c 30.72 32 33.28 mhz v cc = 1.8 v to 5.5 v ? 40 c t opr 85 c 30.40 32 33.60 mhz ? oscillation stability time v cc = 5.0 v, t opr = 25 c?0.53ms ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c ? 400 ? a table 5.13 low-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. foco-s low-speed on-chip oscillator frequency 60 125 250 khz ? oscillation stability time v cc = 5.0 v, t opr = 25 c ? 30 100 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c? 2 ? a table 5.14 power supply circui t timing characteristics symbol parameter condition standard unit min. typ. max. t d(p-r) time for internal power supply stabilization during power-on (2) ? ? 2,000 s
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 40 of 59 nov 02, 2010 notes: 1. v cc = 1.8 to 5.5 v, v ss = 0 v, and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified. 2. 1t cyc = 1/f1(s) table 5.15 timing requirements of sync hronous serial communication unit (ssu) symbol parameter conditions standard unit min. typ. max. t sucyc ssck clock cycle time 4 ? ? t cyc (2) t hi ssck clock ?h? width 0.4 ? 0.6 t sucyc t lo ssck clock ?l? width 0.4 ? 0.6 t sucyc t rise ssck clock rising time master ? ? 1 t cyc (2) slave ? ? 1 s t fall ssck clock falling time master ? ? 1 t cyc (2) slave ? ? 1 s t su sso, ssi data input setup time 100 ? ? ns t h sso, ssi data input hold time 1 ? ? t cyc (2) t lead scs setup time slave 1t cyc + 50 ? ? ns t lag scs hold time slave 1t cyc + 50 ? ? ns t od sso, ssi data output delay time ? ? 1 t cyc (2) t sa ssi slave access time 2.7 v v cc 5.5 v ? ? 1.5t cyc + 100 ns 1.8 v v cc < 2.7 v ? ? 1.5t cyc + 200 ns t or ssi slave out open time 2.7 v v cc 5.5 v ? ? 1.5t cyc + 100 ns 1.8 v v cc < 2.7 v ? ? 1.5t cyc + 200 ns
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 41 of 59 nov 02, 2010 figure 5.4 i/o timing of synchronous serial communication unit (ssu) (master) v ih or v oh v il or v ol t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 1 v ih or v oh v il or v ol t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 0 cphs, cpos: bits in ssmr register
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 42 of 59 nov 02, 2010 figure 5.5 i/o timing of synchronous seri al communication unit (ssu) (slave) v ih or v oh v il or v ol scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 1 v ih or v oh v il or v ol t hi t lo t hi t fall t rise t lo t sucyc t h t su scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 0 t od t lead t sa t lag t or t hi t lo t hi t fall t rise t lo t sucyc t h t su t od t lead t sa t lag t or cphs, cpos: bits in ssmr register
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 43 of 59 nov 02, 2010 figure 5.6 i/o timing of synchronous serial communication unit (ssu) (clock synchronous communication mode) v ih or v oh t hi t lo t sucyc t od t h t su ssck sso (output) ssi (input) v il or v ol
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 44 of 59 nov 02, 2010 notes: 1. v cc = 1.8 to 5.5 v, v ss = 0 v, and t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified. 2. 1t cyc = 1/f1(s) figure 5.7 i/o timing of i 2 c bus interface table 5.16 timing requirements of i 2 c bus interface symbol parameter condition standard unit min. typ. max. t scl scl input cycle time 12t cyc + 600 (2) ??ns t sclh scl input ?h? width 3t cyc + 300 (2) ??ns t scll scl input ?l? width 5t cyc + 500 (2) ??ns t sf scl, sda input fall time ? ? 300 ns t sp scl, sda input spike pulse rejection time ? ? 1t cyc (2) ns t buf sda input bus-free time 5t cyc (2) ??ns t stah start condition input hold time 3t cyc (2) ??ns t stas retransmit start condi tion input setup time 3t cyc (2) ??ns t stop stop condition input setup time 3t cyc (2) ??ns t sdas data input setup time 1t cyc + 40 (2) ??ns t sdah data input hold time 10 ? ? ns sda scl notes: 1. start condition 2. stop condition 3. retransmit start condition t buf v ih v il p (2) s (1) t stah t sclh t scll t sf t sr t scl t sdah sr (3) p (2) t sdas t stas t sp t stop
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 45 of 59 nov 02, 2010 note: 1. 4.2 v v cc 5.5 v, t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), and f(xin) = 20 mhz, unless otherwise specified. table 5.17 electrical characteristics (1) [4.2 v v cc 5.5 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage other than xout drive capacity high v cc = 5 v i oh = ? 20 ma v cc ? 2.0 ? v cc v drive capacity low v cc = 5 v i oh = ? 5 ma v cc ? 2.0 ? v cc v xout v cc = 5 v i oh = ? 200 a1.0 ? v cc v v ol output ?l? voltage other than xout drive capacity high v cc = 5 v i ol = 20 ma ? ? 2.0 v drive capacity low v cc = 5 v i ol = 5 ma ? ? 2.0 v xout v cc = 5 v i ol = 200 a? ?0.5v v t+- v t- hysteresis int0 , int1 , int2 , int3 , int4 , ki0 , ki1 , ki2 , ki3 , traio, trbo, trcioa, trciob, trcioc, trciod, trdioa0, trdiob0, trdioc0, trdiod0, trdioa1, trdiob1, trdioc1, trdiod1, trctrg, trcclk, trfi, trgioa, trgiob, adtrg , rxd0, rxd1, rxd2, clk0, clk1, clk2, ssi, scl, sda, sso 0.1 1.2 ? v reset 0.1 1.2 ? v i ih input ?h? current v i = 5 v, v cc = 5.0 v ? ? 5.0 a i il input ?l? current v i = 0 v, v cc = 5.0 v ? ? ? 5.0 a r pullup pull-up resistance v i = 0 v, v cc = 5.0 v 25 50 100 k ? r fxin feedback resistance xin ? 0.3 ? m ? r fxcin feedback resistance xcin ? 8 ? m ? v ram ram hold voltage during stop mode 1.8 ? ? v
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 46 of 59 nov 02, 2010 table 5.18 electrical characteristics (2) [3.3 v v cc 5.5 v] (t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 3.3 to 5.5 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ?6.515ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 5.3 12.5 ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ?3.6?ma xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ?3.0?ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ?2.2?ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ?1.5?ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco-f = 20 mhz low-speed on-chip oscillator on = 125 khz no division ?7.015ma xin clock off high-speed on-chip oscillator on foco-f = 20 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ?3.0?ma xin clock off high-speed on-chip oscillator on foco-f = 4 mhz low-speed on-chip oscillator on = 125 khz divide-by-16, mstiic = msttrd = msttrc = 1 ?1?ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr27 = 1, vca20 = 0 ?90400 a low-speed clock mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz no division fmr27 = 1, vca20 = 0 ?85400 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz no division program operation on ram flash memory off, fmstp = 1, vca20 = 0 ?47? a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0, vca20 = 1 ?15100 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0, vca20 = 1 ?490 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (peripheral clock off) while a wait instruction is executed vca27 = vca26 = vca25 = 0, vca20 = 1 ?3.5? a stop mode xin clock off, t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ?2.05.0 a xin clock off, t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ?15? a
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 47 of 59 nov 02, 2010 timing requirements (unless otherwise specified: v cc = 5 v, v ss = 0 v, t opr = 25 c) figure 5.8 external clock input timing diagram when vcc = 5 v figure 5.9 traio input timing diagram when v cc = 5 v notes: 1. when using timer rf input capture mode, adjust the cycle time to (1/timer rf count source frequency 3) or above. 2. when using timer rf input capture mode, adjust the pulse width to (1/timer rf count source frequency 1.5) or above. figure 5.10 trfi input timing diagram when v cc = 5 v table 5.19 external clock input (xout, xcin) symbol parameter standard unit min. max. t c(xout) xout input cycle time 50 ? ns t wh(xout) xout input ?h? width 24 ? ns t wl(xout) xout input ?l? width 24 ? ns t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7 ? s table 5.20 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 100 ? ns t wh(traio) traio input ?h? width 40 ? ns t wl(traio) traio input ?l? width 40 ? ns table 5.21 trfi input symbol parameter standard unit min. max. t c(trfi) trfi input cycle time 400 (1) ?ns t wh(trfi) trfi input ?h? width 200 (2) ?ns t wl(trfi) trfi input ?l? width 200 (2) ?ns external clock input t wh(xout), t wh(xcin) t c(xout), t c(xcin) t wl(xout), t wl(xcin) v cc = 5 v traio input v cc = 5 v t c(traio) t wl(traio) t wh(traio) t wh(trfi) t c(trfi) t wl(trfi) trfi input v cc = 5 v
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 48 of 59 nov 02, 2010 i = 0 to 2 figure 5.11 serial interface timing diagram when v cc = 5 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.12 input timing diagram for external interrupt inti and key input interrupt kii when v cc = 5 v table 5.22 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 200 ? ns t w(ckh) clki input ?h? width 100 ? ns t w(ckl) clki input ?l? width 100 ? ns t d(c-q) txdi output delay time ? 50 ns t h(c-q) txdi hold time 0?ns t su(d-c) rxdi input setup time 50 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.23 external interrupt inti (i = 0 to 4) input, key input interrupt kii (i = 0 to 3) symbol parameter standard unit min. max. t w(inh) inti input ?h? width, kii input ?h? width 250 (1) ?ns t w(inl) inti input ?l? width, kii input ?l? width 250 (2) ?ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi i = 0 to 2 v cc = 5 v inti input (i = 0 to 4) t w(inl) t w(inh) v cc = 5 v kii input (i = 0 to 3)
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 49 of 59 nov 02, 2010 note: 1. 2.7 v v cc < 4.2 v, t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), and f(xin) = 10 mhz, unless otherwise specified. table 5.24 electrical characteristics (3) [2.7 v v cc < 4.2 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage other than xout drive capacity high i oh = ? 5 ma v cc ? 0.5 ? v cc v drive capacity low i oh = ? 1 ma v cc ? 0.5 ? v cc v xout i oh = ? 200 a1.0 ? v cc v v ol output ?l? voltage other than xout drive capacity high i ol = 5 ma ? ? 0.5 v drive capacity low i ol = 1 ma ? ? 0.5 v xout i ol = 200 a? ?0.5v v t+- v t- hysteresis int0 , int1 , int2 , int3 , int4 , ki0 , ki1 , ki2 , ki3 , traio, trbo, trcioa, trciob, trcioc, trciod, trdioa0, trdiob0, trdioc0, trdiod0, trdioa1, trdiob1, trdioc1, trdiod1, trctrg, trcclk, trfi, trgioa, trgiob, adtrg , rxd0, rxd1, rxd2, clk0, clk1, clk2, ssi, scl, sda, sso v cc = 3.0 v 0.1 0.4 ? v reset v cc = 3.0 v 0.1 0.5 ? v i ih input ?h? current v i = 3 v, v cc = 3.0 v ? ? 4.0 a i il input ?l? current v i = 0 v, v cc = 3.0 v ? ? ? 4.0 a r pullup pull-up resistance v i = 0 v, v cc = 3.0 v 42 84 168 k ? r fxin feedback resistance xin ? 0.3 ? m ? r fxcin feedback resistance xcin ? 8 ? m ? v ram ram hold voltage during stop mode 1.8 ? ? v
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 50 of 59 nov 02, 2010 table 5.25 electrical characteristics (4) [2.7 v v cc 3.3 v] (t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 2.7 to 3.3 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ?3.510ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ?1.57.5ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco-f = 20 mhz low-speed on-chip oscillator on = 125 khz no division ?7.015ma xin clock off high-speed on-chip oscillator on foco-f = 20 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ?3.0?ma xin clock off high-speed on-chip oscillator on foco-f = 10 mhz low-speed on-chip oscillator on = 125 khz no division ?4.0?ma xin clock off high-speed on-chip oscillator on foco-f = 10 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ?1.5?ma xin clock off high-speed on-chip oscillator on foco-f = 4 mhz low-speed on-chip oscillator on = 125 khz divide-by-16, mstiic = msttrd = msttrc = 1 ?1?ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr27 = 1, vca20 = 0 ?90390 a low-speed clock mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz no division fmr27 = 1, vca20 = 0 ?80400 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz no division program operation on ram flash memory off, fmstp = 1, vca20 = 0 ?40? a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instr uction is executed peripheral clock operation vca27 = vca26 = vca25 = 0, vca20 = 1 ?1590 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instr uction is executed peripheral clock off vca27 = vca26 = vca25 = 0, vca20 = 1 ?480 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (peripheral clock off) while a wait instr uction is executed vca27 = vca26 = vca25 = 0, vca20 = 1 ?3.5? a stop mode xin clock off, t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ?2.05.0 a xin clock off, t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ?15? a
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 51 of 59 nov 02, 2010 timing requirements (unless otherwise specified: v cc = 3 v, v ss = 0 v, t opr = 25 c) figure 5.13 external clock input timing diagram when vcc = 3 v figure 5.14 traio input ti ming diagram when v cc = 3 v notes: 1. when using timer rf input capture mode, adjust the cycle time to (1/timer rf count source frequency 3) or above. 2. when using timer rf input capture mode, adjust the pulse width to (1/timer rf count source frequency 1.5) or above. figure 5.15 trfi input timing diagram when v cc = 3 v table 5.26 external clock input (xout, xcin) symbol parameter standard unit min. max. t c(xout) xout input cycle time 50 ? ns t wh(xout) xout input ?h? width 24 ? ns t wl(xout) xout input ?l? width 24 ? ns t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7? s table 5.27 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 300 ? ns t wh(traio) traio input ?h? width 120 ? ns t wl(traio) traio input ?l? width 120 ? ns table 5.28 trfi input symbol parameter standard unit min. max. t c(trfi) trfi input cycle time 1200 (1) ?ns t wh(trfi) trfi input ?h? width 600 (2) ?ns t wl(trfi) trfi input ?l? width 600 (2) ?ns external clock input t wh(xout), t wh(xcin) t c(xout), t c(xcin) t wl(xout), t wl(xcin) v cc = 3 v traio input v cc = 3 v t c(traio) t wl(traio) t wh(traio) t wh(trfi) t c(trfi) t wl(trfi) trfi input v cc = 3 v
r8c/36c group 5. electri cal characteristics r01ds0018ej0110 rev.1.10 page 52 of 59 nov 02, 2010 i = 0 to 2 figure 5.16 serial interface timing diagram when v cc = 3 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.17 input timing diagram for external interrupt inti and key input interrupt kii when v cc = 3 v table 5.29 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 300 ? ns t w(ckh) clki input ?h? width 150 ? ns t w(ckl) clki input ?l? width 150 ? ns t d(c-q) txdi output delay time ? 80 ns t h(c-q) txdi hold time 0?ns t su(d-c) rxdi input setup time 70 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.30 external interrupt inti (i = 0 to 4) input, key input interrupt kii (i = 0 to 3) symbol parameter standard unit min. max. t w(inh) inti input ?h? width, kii input ?h? width 380 (1) ?ns t w(inl) inti input ?l? width, kii input ?l? width 380 (2) ?ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi v cc = 3 v i = 0 to 2 t w(inl) t w(inh) v cc = 3 v inti input (i = 0 to 4) kii input (i = 0 to 3)
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 53 of 59 nov 02, 2010 note: 1. 1.8 v v cc < 2.7 v, t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), and f(xin) = 5 mh z, unless otherwi se specified. table 5.31 electrical characteristics (5) [1.8 v v cc < 2.7 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage other than xout drive capacity high i oh = ? 2 ma v cc ? 0.5 ? v cc v drive capacity low i oh = ? 1 ma v cc ? 0.5 ? v cc v xout i oh = ? 200 a1.0 ? v cc v v ol output ?l? voltage other than xout drive capacity high i ol = 2 ma ? ? 0.5 v drive capacity low i ol = 1 ma ? ? 0.5 v xout i ol = 200 a? ?0.5v v t+- v t- hysteresis nt0 , int1 , int2 , int3 , int4 , ki0 , ki1 , ki2 , ki3 , traio, trbo, trcioa, trciob, trcioc, trciod, trdioa0, trdiob0, trdioc0, trdiod0, trdioa1, trdiob1, trdioc1, trdiod1, trctrg, trcclk, trfi, trgioa, trgiob, adtrg , rxd0, rxd1, rxd2, clk0, clk1, clk2, ssi, scl, sda, sso 0.05 0.20 ? v reset 0.05 0.20 ? v i ih input ?h? current v i = 2.2 v, v cc = 2.2 v ? ? 4.0 a i il input ?l? current v i = 0 v, v cc = 2.2 v ? ? ? 4.0 a r pullup pull-up resistance v i = 0 v, v cc = 2.2 v 70 140 300 k ? r fxin feedback resistance xin ? 0.3 ? m ? r fxcin feedback resistance xcin ? 8 ? m ? v ram ram hold voltage during stop mode 1.8 ? ? v
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 54 of 59 nov 02, 2010 table 5.32 electrical characteristics (6) [1.8 v v cc < 2.7 v] (t opr = ? 20 to 85 c (n version)/ ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 1.8 to 2.7 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 5 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ?2.2?ma xin = 5 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ?0.8?ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco-f = 5 mhz low-speed on-chip oscillator on = 125 khz no division ?2.510ma xin clock off high-speed on-chip oscillator on foco-f = 5 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ?1.7?ma xin clock off high-speed on-chip oscillator on foco-f = 4 mhz low-speed on-chip oscillator on = 125 khz divide-by-16, mstiic = msttrd = msttrc = 1 ?1?ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr27 = 1, vca20 = 0 ?90300 a low-speed clock mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz no division fmr27 = 1, vca20 = 0 ?80350 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz no division program operation on ram flash memory off, fmstp = 1, vca20 = 0 ?40? a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instr uction is executed peripheral clock operation vca27 = vca26 = vca25 = 0, vca20 = 1 ?1590 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instr uction is executed peripheral clock off vca27 = vca26 = vca25 = 0, vca20 = 1 ?480 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (peripheral clock off) while a wait instr uction is executed vca27 = vca26 = vca25 = 0, vca20 = 1 ?3.5? a stop mode xin clock off, t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ?2.0 5 a xin clock off, t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ?15? a
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 55 of 59 nov 02, 2010 timing requirements (unless otherwise specified: v cc = 2.2 v, v ss = 0 v, t opr = 25 c) figure 5.18 external clock input timing diagram when vcc = 2.2 v figure 5.19 traio input ti ming diagram when v cc = 2.2 v notes: 1. when using timer rf input capture mode, adjust the cycle time to (1/timer rf count source frequency 3) or above. 2. when using timer rf input capture mode, adjust the pulse width to (1/timer rf count source frequency 1.5) or above. figure 5.20 trfi input timing diagram when v cc = 2.2 v table 5.33 external clock input (xout, xcin) symbol parameter standard unit min. max. t c(xout) xout input cycle time 200 ? ns t wh(xout) xout input ?h? width 90 ? ns t wl(xout) xout input ?l? width 90 ? ns t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7? s table 5.34 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 500 ? ns t wh(traio) traio input ?h? width 200 ? ns t wl(traio) traio input ?l? width 200 ? ns table 5.35 trfi input symbol parameter standard unit min. max. t c(trfi) trfi input cycle time 2000 (1) ?ns t wh(trfi) trfi input ?h? width 1000 (2) ?ns t wl(trfi) trfi input ?l? width 1000 (2) ?ns external clock input t wh(xout), t wh(xcin) t c(xout), t c(xcin) t wl(xout), t wl(xcin) v cc = 2.2 v traio input t c(traio) t wl(traio) t wh(traio) v cc = 2.2 v t wh(trfi) t c(trfi) t wl(trfi) trfi input v cc = 2.2 v
r8c/36c group 5. electrical characteristics r01ds0018ej0110 rev.1.10 page 56 of 59 nov 02, 2010 i = 0 to 2 figure 5.21 serial interface timing diagram when v cc = 2.2 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.22 input timing diagram for external interrupt inti and key input interrupt kii when v cc = 2.2 v table 5.36 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 800 ? ns t w(ckh) clki input ?h? width 400 ? ns t w(ckl) clki input ?l? width 400 ? ns t d(c-q) txdi output delay time ? 200 ns t h(c-q) txdi hold time 0?ns t su(d-c) rxdi input setup time 150 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.37 external interrupt inti (i = 0 to 4) input, key input interrupt kii (i = 0 to 3) symbol parameter standard unit min. max. t w(inh) inti input ?h? width, kii input ?h? width 1000 (1) ?ns t w(inl) inti input ?l? width, kii input ?l? width 1000 (2) ?ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi v cc = 2.2 v i = 0 to 2 t w(inl) t w(inh) v cc = 2.2 v inti input (i = 0 to 4) kii input (i = 0 to 3)
r8c/36c group package dimensions r01ds0018ej0110 rev.1.10 page 57 of 59 nov 02, 2010 package dimensions diagrams showing the latest package dimensions and moun ting information are available in the ?p ackages? section of the renesas electronics website. terminal cross section b 1 c 1 b p c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. index mark * 3 17 32 64 49 116 33 48 f * 1 * 2 x b p h e e h d d z d z e detail f a c a 2 a 1 l 1 l p-lqfp64-10x10-0.50 0.3g mass[typ.] 64p6q-a / fp-64k / fp-64kv plqp0064kb-a renesas code jeita package code previous code 1.0 0.125 0.18 1.25 1.25 0.08 0.20 0.145 0.09 0.25 0.20 0.15 max nom min dimension in millimeters symbol reference 10.1 10.0 9.9 d 10.1 10.0 9.9 e 1.4 a 2 12.2 12.0 11.8 12.2 12.0 11.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.08 y h d h e a 1 b p b 1 c 1 z d z e l 1 e y s s
r8c/36c group package dimensions r01ds0018ej0110 rev.1.10 page 58 of 59 nov 02, 2010 terminal cross section b1 c1 bp c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. * 3 116 17 32 33 48 49 64 f * 1 * 2 x index mark d h d e h e e b p z d z e detail f c a a 2 a 1 l l 1 previous code jeita package code renesas code plqp0064ga-a 64p6u-a/ ? mass[typ.] 0.7g p-lqfp64-14x14-0.80 1.0 0.125 0.35 1.0 1.0 0.20 0.20 0.145 0.09 0.42 0.37 0.32 max nom min dimension in millimeters symbol reference 14.1 14.0 13.9 d 14.1 14.0 13.9 e 1.4 a 2 16.2 16.0 15.8 16.2 16.0 15.8 1.7 a 0.2 0.1 0 0.7 0.5 0.3 l x 8 0 c 0.8 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 y s s
r8c/36c group package dimensions r01ds0018ej0110 rev.1.10 page 59 of 59 nov 02, 2010 s s y f xm * 3 e b p detail f c a l a 1 a 2 l 1 note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. terminal cross section c c 1 b p b 1 1.00 1.20 1.00 0 8 0.40 0.12 0.17 0.22 0.15 0.16 0.13 0.18 0.23 8.8 9.0 9.2 6.9 7.0 7.1 6.9 7.0 7.1 0.50 9.2 9.0 8.8 0.10 0.08 0.07 reference symbol dimension in millimeters min nom max e h e l a 1 d e a 2 h d a b p b 1 c x y z d z e l 1 c 1 0.05 0.15 0.50 0.50 0.35 0.65 previous code jeita package code renesas code ptqp0064lb-a ? mass[typ.] 0.14g p-tqfp64-7x7-0.40 1 64 17 16 49 48 33 32 * 2 * 1 e d h d z d h e z e
r8c/36c group datasheet c - 1 rev. date description page summary 0.01 oct 30, 2009 ? first edition issued 1.00 nov 02, 2010 all pages ?preliminary?, ?under development? deleted 4 table 1.3 revised 28 to 54 ?5. electrical characteristics? added 1.10 nov 02, 2010 ? tn-r8c-a015a/e reflected 3 table 1.2 ?timer rg? and ?package? revised 4 and 5 tables 1.3 and 1.4 revised 6 figure 1.1 revised 8 figure 1.3 ?ptqp0064lb-a? added 17 figure 3.1 ?part number? revised 33 table 5.3 ?tconv?, ?tsamp? revised 47 table 5.21 revised 51 table 5.28 revised 55 table 5.35 revised 59 package (ptqp0064lb-a) added all trademarks and registered trademarks are the property of their respective owners. revision history
general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manu al. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the bod y of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directi ons given under handling of unused pins in the manual. ? the input pins of cmos products are general ly in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through cu rrent flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at t he moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a pr oduct that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the po ssible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during pr ogram execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset li ne is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different part numbe rs, implement a system-evaluation test for each of the products.
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